MBM29F400BC-55PF SPANSION [SPANSION], MBM29F400BC-55PF Datasheet - Page 18

• Manufacturer Part Number: MBM29F400BC-55PF
• Description: FLASH MEMORY CMOS 4M (512K x 8/256K x 16) BIT
• Manufacturer: SPANSION [SPANSION]

Write Operation Status
*1 : Performing successive read operations from any address will cause DQ
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
Notes:
DQ
Data Polling
In
Progress
Exceeded
Time
Limits
The MBM29F400TC/BC device feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device
will produce the complement of the data last written to DQ
Algorithm, an attempt to read the device will produce the true data last written to DQ
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
for Data Polling (DQ
For Programing, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29F400TC/BC data pins (DQ
enable (OE) is asserted low. This means that the device is driving status information on DQ
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation
and DQ
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out (See “Hardware Sequence Flags”).
See “AC Waveforms for Data Polling during Embedded Algorithm Operations” in TIMING DIAGRAM for the
Data Polling timing specifications and diagrams.
7
at the DQ
MBM29F400TC
DQ
DQ
7
has a valid data, the data outputs on DQ
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
2
0
15
and DQ
bit. However, successive reads from the erase-suspended sector will cause DQ
to DQ
8
7
1
are “DON’T CARES” because there is for
) is shown in “Data Polling Algorithm” in FLOW CHART.
are reserve pins for future use. DQ
Erase Suspend Read
(Erase Suspended Sector)
Erase Suspend Read
Erase Suspend Program
Erase Suspend Program (Non-Erase
Suspended Sector)
(Non-Erase Suspended Sector)
(Non-Erase Suspended Sector)
Status
-55/-70-90
Hardware Sequence Flags
6
to DQ
/MBM29F400BC
0
4
may be still invalid. The valid data on DQ
is Fujitsu internal use only.
7
. Upon completion of the Embedded Program
7
) may change asynchronously while the output
16 mode.
Data
DQ
DQ
DQ
DQ
DQ
0
1
0
7
7
7
7
7
6
to toggle.
7
Toggle*
output. Upon completion of the
Toggle
Toggle
Toggle
Toggle
Toggle
Data
DQ
1
6
1
7
. During the Embedded
7
Data
DQ
output. The flowchart
0
0
0
0
1
1
1
5
7
2
-55/-70-90
at one instant of
to toggle.
Data
DQ
0
1
0
0
0
1
0
7
3
to DQ
Toggle
Toggle
Data
DQ
N/A
N/A
1*
1
1
0
2
will
2
7
17