S29PL-N SPANSION [SPANSION], S29PL-N Datasheet - Page 77

• Manufacturer Part Number: S29PL-N
• Description: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

12.1
November 23, 2005 S29PL-N_00_A4
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The data is 0000h for an unlocked sector and 0001h for a locked
11. Device IDs: PL256N = 223Ch; PL127N = 2220h;
12. See Autoselect.
13. The Unlock Bypass command sequence is required prior to this
14. The Unlock Bypass Reset command is required to return to
See
All values are in hexadecimal.
Except for the following, all bus cycles are write cycle: read
cycle, fourth through sixth cycles of the Autoselect commands,
and password verify commands, and any cycle reading at RD(0)
and RD(1).
Data bits DQ15 – DQ8 are don’t care in command sequences,
except for RD, PD, WD, PWD, and PWD3 – PWD0.
Unless otherwise noted, these address bits are don’t cares:
PL127: A22 – A15; 129N: A21 – A15; PL256N: A23 – A14.
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
No unlock or command cycles required when bank is reading
array data.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See
Autoselect.
sector.
PL129N = 2221h.
command sequence.
reading array data when the bank is in the unlock bypass
mode.The system may read and program in non-erasing sectors,
or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
(Table
Common Flash Memory Interface
7.1) for description of bus operations.
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI in-
formation at the addresses given in Tables
CFI address range, within the bank, return non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available at
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
/* Example: CFI Exit command */
*((UINT16 *)bank_addr + 0x555) = 0x0098;
*((UINT16 *)bank_addr + 0x000) = 0x00F0;
P r e l i m i n a r y
S29PL-N MirrorBit™ Flash Family
/* write CFI entry command
/* write cfi exit command
15. The Erase Resume command is valid only during the Erase
16. Command is valid when device is ready to read array data or
17. The entire four bus-cycle sequence must be entered for which
18. The Unlock Bypass Reset command is required to return to
19. The Erase Resume command is valid only during the Erase
20. Command is valid when device is ready to read array data or
21. The entire four bus-cycle sequence must be entered for which
22. The ALL PPB ERASE command pre-programs all PPBs before
23. WP#/ACC must be at VHH during the entire operation of this
24. Command sequence resets device for next command after write-
25. Entry commands are needed to enter a specific mode to enable
26. If both the Persistent Protection Mode Locking Bit and the
27. The Exit command must be issued to reset the device into read
12.3
Suspend mode, and requires the bank address.
when device is in autoselect mode.The total number of cycles in
the command sequence is determined by the number of words
written to the write buffer. The maximum number of cycles in
the command sequence is 37.
portion of the password.
reading array data when the bank is in the unlock bypass
mode.The system may read and program in non-erasing sectors,
or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
Suspend mode, and requires the bank address.
when device is in autoselect mode.The total number of cycles in
the command sequence is determined by the number of words
written to the write buffer. The maximum number of cycles in
the command sequence is 37.
portion of the password.
erasure to prevent over-erasure of PPBs.
command.
to-buffer operation.
instructions only available within that mode.
password Protection Mode Locking Bit are set a the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode.
mode. Otherwise the device hangs.
– 12.6) within that bank. All reads outside of the
www.amd.com
*/
*/
and
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