CYP15G0101 CYPRESS [Cypress Semiconductor], CYP15G0101 Datasheet - Page 27

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CYP15G0101

Manufacturer Part Number
CYP15G0101
Description
Single-channel HOTLink Transceiver
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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Document #: 38-02031 Rev. *I
Switching Waveforms for the HOTLink II Transmitter
Notes:
37. When REFCLK is configured for half-rate operation (TXRATE
38. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the
39. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = LOW
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = HIGH
TXCT[1:0],
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = HIGH
TXCT[1:0],
Transmit Interface
Write Timing
TXCKSEL ¹ LOW
TXD[7:0],
TXD[7:0],
is captured using both the rising and falling edges of REFCLK.
duty cycle of REFCLK.
REFCLK
TXCT[1:0],
SCSEL
TXCLK
SCSEL
TXD[7:0],
TXOP,
TXOP,
REFCLK
SCSEL
TXOP,
REFCLK
TXCLKO
Note 39
Note 37
t
t
t
TXCLKH
REFH
TREFDH
t
TXCLKOD+
t
t
REFCLK
TXCLK
t
t
REFH
TXCLKO
=
t
REFH
HIGH) and data is captured using REFCLK instead of TXCLK clock (TXCKSEL
t
TREFDS
t
t
TXCLKL
REFL
t
Note 38
t
TXCLKOD–
TXDS
t
TREFDS
t
REFCLK
Note 37
t
REFCLK
t
t
TREFDH
TXDH
t
TREFDH
t
REFL
t
REFL
t
CYP15G0101DXB
CYV15G0101DXB
TREFDS
Page 27 of 39
=
LOW), data

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