CYP15G0101 CYPRESS [Cypress Semiconductor], CYP15G0101 Datasheet - Page 39

• Manufacturer Part Number: CYP15G0101
• Description: Single-channel HOTLink Transceiver
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-02031 Rev. *I
Document History Page
Document Title: CYP(V)15G0101DXB Single-channel HOTLink II™ Transceiver
Document Number: 38-02031
REV.
*G
*A
*B
*C
*D
*E
*F
*H
**
*I
ECN NO.
113123
119704
122209
122546
124994
128366
128835
131898
211461
230621
Issue Date
See ECN
See ECN
05/20/02
10/30/02
12/28/02
02/13/03
04/15/03
12/10/03
7/31/03
7/3/03
Change
Orig. of
LNM
CGX
POT
PDS
TPS
PDS
KKV
KKV
LAR
RBI
New Data Sheet
Changed TXPER description
Changed TXCLKO description
Changed RXCKSEL to include RXCLKC+
Removed disparity reference from RFMODE
Removed the LOW setting for FRAMCHAR and related references
Removed references to ATM transport
Changed the I
Changed V
Changed the t
Changed t
Changed t
Changed the JTAG ID from 0C804069 to 1C804069
Added a section for characterization and standards compliance
Changed I/O type of RXCLKC in I/O coordinates table
Minor Change Document Control corrected Document History Page
Changed Minimum tRISE/tFALL for CML
Changed tRXLOCK
Changed tDJ, tRJ
Changed tJTOL
Changed tTXLOCK
Changed tRXCLKH, tRXCLKL
Changed tTXCLKOD+, tTXCLKOD-
Changed Power Specs
Changed verbiage...Paragraph: Clock/Data Recovery
Changed verbiage...Paragraph: Range Control
Added Power-up Requirements
Changed CYP15G0101DXB to CYP(V)15G0101DXB type corresponding to
the Video-compliant parts
Reduced the lower limit of the serial signaling rate from 200 Mbaud to
195 Mbaud and changed the associated specifications accordingly
Revised the value of t
Minor change: corrections due to editorial error - old file used for *E revision
(reestablishing *D changes)
When TXCKSEL = MID or HIGH, TXRATE = HIGH is an invalid mode. Made
appropriate changes to reflect this invalid condition
Removed requirement of AC coupling for Serial I/Os for interfacing with
LVPECL I/Os
Changed LFI to Asynchronous output
Expanded the CDR Range Controller’s permissible frequency offset
between incoming serial signaling rate and Reference clock from ±200-PPM
to ±1500-PPM (changed parameter t
Minor change: Package diagram isn’t legible in pdf.
Updated package information in features list to reflect correct package
TXDS
REFDV–
ODIF
OST
TXCLKR
, t
and V
TXDH
, t
boundary values
REFCDV–
OLC
and t
, t
RREFDV,
TREFDS
for CML output
Description of Change
TXCLKF
, and t
t
, and t
REFADV+ and
min. values
REFCDV+
TREFDH
REFRX
t
REFCDV+
)
CYP15G0101DXB
CYV15G0101DXB
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