CYP15G0101 CYPRESS [Cypress Semiconductor], CYP15G0101 Datasheet - Page 3
![no-image](/images/no-image-200.jpg)
CYP15G0101
Manufacturer Part Number
CYP15G0101
Description
Single-channel HOTLink Transceiver
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CYP15G0101.pdf
(39 pages)
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Document #: 38-02031 Rev. *I
Logic Block Diagram
FRAMCHAR
TXMODE[1:0]
DECMODE
RXCKSEL
RXMODE
RFMODE
SDASEL
REFCLK+
REFCLK–
TXCLKO+
TXCLKO–
RXRATE
TXCT[1:0]
TXCKSEL
BOE[1:0]
TXRATE
SPDSEL
TXD[7:0]
INSEL
RFEN
TXPER
SCSEL
PARCTL
LPEN
TXRST
TXLB
TXCLK
RXLE
IN1+
IN1–
IN2+
IN2–
TXOP
Character-Rate Clock
2
8
2
H M L
Clock Multiplier
Character-Rate Clock
Transmit PLL
RX PLL Enable
Recovery
Receive
Monitor
Clock &
Signal
Data
PLL
Latch
12
Transmit
Mode
12
Bit-Rate Clock
12
Select
Clock
BIST Enable
Latch
Boundary
Controller
4
JTAG
10
Scan
Character-Rate Clock
¸2
Enable
Output
Latch
Delay
CYP15G0101DXB
CYV15G0101DXB
3
8
2
= Internal Signal
RXCLKC+
RXD[7:0]
RXOP
RXST[2:0]
RXCLK+
RXCLK–
TRSTZ
LFI
TMS
TCLK
TDI
TDO
Page 3 of 39
OELE
BISTLE
OUT1+
OUT1–
OUT2+
OUT2–
TXLB