CY7B923-400JI CYPRESS [Cypress Semiconductor], CY7B923-400JI Datasheet - Page 13

• Manufacturer Part Number: CY7B923-400JI
• Manufacturer: CYPRESS [Cypress Semiconductor]

HOTLink CY7B923 Transmitter and CY7B933
Receiver Operation
The CY7B923 Transmitter operating with the CY7B933 Re-
ceiver form a general purpose data communications sub-
system capable of transporting user data at up to 33Mbytes
per second (40 Mbytes per second for -400 devices) over sev-
eral types of serial interface media. Figure 2 illustrates the flow
of data through the HOTLink CY7B923 transmitter pipeline. Data is
latched into the transmitter on the rising edge of CKW when enabled
by ENA or ENN. RP is asserted LOW with a 60% LOW/40% HIGH
duty cycle when ENA is LOW. RP may be used as a read strobe for
accessing data stored in a FIFO. The parallel data flows through the
encoder and is then shifted out of the OUTx PECL drivers. The
bit-rate clock is generated internally from a multiply-by-ten PLL clock
generator. The latency through the transmitter is approximately 21tB
found in the section CY7B923 HOTLink Transmitter Operating Mode
Description .
Figure 3 illustrates the data flow through the HOTLink
CY7B933 receiver pipeline. Serial data is sampled by the re-
10 ns over the operating range. A more complete description is
D0 7,
SC/D,
SVS
OUTX
ENA
CKW
RP
Q0 7,
SC/D,
RVS
RDY
CKR
INX
SERIAL DATA IN
RDY IS LOW FOR DATA
DATA LATCHED IN
DATA
Figure 3. CY7B933 Receiver Data Pipeline in Encoded Mode
DATA
DATA
Figure 2. CY7B923 Transmitter Data Pipeline
RDY IS HIGH IN FIELD OF K28.5S
RECEIVER LATENCY= 24 t
K28.5
TRANSMITTER LATENCY = 21 t
K28.5
13
ceiver on the INx inputs. The receiver PLL locks onto the
serial bit stream and generates an internal bit rate clock. The
bit stream is deserialized, decoded and then presented at the
parallel output pins. A byte rate clock (bit clock
nous with the parallel data is presented at the CKR pin. The
RDY pin will be asserted to LOW to indicate that data or control
characters are present on the outputs. RDY will not be assert-
ed LOW in a field of K28.5s except for any single K28.5 or the
last one in a continuous series of K28.5’s. The latency through
the receiver is approximately 24t
range. A more complete description of the receiver is in the
section CY7B933 HOTLink Receiver Operating Mode De-
scription
The HOTLink Receiver has a built-in byte framer that synchro-
nizes the Receiver pipeline with incoming SYNC (K28.5) char-
acters. Figure 4 illustrates the HOTLink CY7B933 Receiver framing
operation. The Framer is enabled when the RF pin is asserted HIGH.
RF is latched into the receiver on the falling edge of CKR. The framer
looks for K28.5 characters embedded in the serial data stream. When
a K28.5 is found, the framer sets the parallel byte boundary for sub-
sequent data to the K28.5 boundary. While the framer is enabled, the
RDY pin indicates the status of the framing operation.
B
+ 10 ns
RDY IS LOW FOR LAST K28.5
DATA SENT
K28.5
B
K28.5
10ns
B
+ 10 ns over the operating
DATA
PARALLEL
DATA OUT
B923–19
CY7B923
CY7B933
B923–18
DATA
10) synchro-