CY7B923-400JI CYPRESS [Cypress Semiconductor], CY7B923-400JI Datasheet - Page 19

• Manufacturer Part Number: CY7B923-400JI
• Manufacturer: CYPRESS [Cypress Semiconductor]

er PLL data synchronizer (one per 10 bit byte) and that it be com-
patible with the transmission media.
The framer function in Bypass mode is identical to Encoded
mode, so a K28.5 pattern can still be used to re-frame the
serial bit stream.
Parallel Output Function
The 10 outputs (Q
ly, and are aligned with RDY and CKR with timing allowances to
interface directly with either an asynchronous FIFO or a clocked
FIFO. Typical FIFO connections are shown in Figure 5 .
Data outputs can be clocked into the system using either the
rising or falling edge of CKR, or the rising or falling edge of
RDY. If CKR is used, RDY can be used as an enable for the receiv-
ing logic. A LOW pulse on RDY shows that new data has been
received and is ready to be delivered. The signal on RDY is a
60% LOW duty cycle byte-rate pulse train suitable for the write
pulse in asynchronous FIFOs such as the CY7C42X, or the enable
write input on Clocked FIFOs such as the CY7C44X. HIGH on RDY
shows that the received data appearing at the outputs is the null
character (normally inserted by the transmitter as a pad between
data inputs) and should be ignored.
When the Transmitter is disabled it will continuously send pad
characters (K28.5). To assure that the receive FIFO will not
be overfilled with these dummy bytes, the RDY pulse output is
inhibited during fill strings. Data at the Q
correct received data, but will not appear to change, since a string
of K28.5s all are decoded as Q7 0 =000 00101 and SC/D = 1
(C5.0). When new data appears (not K28.5), the RDY output will
resume normal function. The “last” K28.5 will be accompanied by
a normal RDY pulse.
Fill characters are defined as any K28.5 followed by another
K28.5. All fill characters will not cause RDY to pulse. Any K28.5
followed by any other character (including violation or illegal charac-
ters) will be interpreted as usable data and will cause RDY to pulse.
As noted above, RDY can also be used as an indication of correct
framing of received data. While the Receiver is awaiting receipt of
a K28.5 with RF HIGH, the RDY outputs will be inhibited. When
RDY resumes, the received data will be properly framed and will be
decoded correctly. In Bypass mode with RF HIGH, RDY will pulse
once for each K28.5 received. For more information on the RDY
pin, consult the “HOTLink CY7B933 RDY Pin Description” applica-
tion note.
Code rule violations and reception errors will be indicated as
follows:
0 7
, SC/D, and RVS) all transition simultaneous-
0 7
outputs will reflect the
19
Receiver Serial Data Requirements
The CY7B933 HOTLink Receiver serial input capability con-
forms to the requirements of the Fibre Channel specification.
The serial data input is tracked by an internal Phase-Locked
Loop that is used to recover the clock phase and to extract the
data from the serial bit stream. Jitter tolerance characteristics
(including both PLL and logic component requirements) are
shown below:
1. Good Data code received
2. Good Special Character
3. K28.7 immediately following
4. K28.7 immediately following
5. Unassigned code received
6. K28.5+ received when
7. +K28.5 received when
8. Good code received
• Deterministic Jitter tolerance (D
• Random Jitter tolerance (R
• Total Jitter tolerance >90% of t
• PLL-Acquisition time <500-bit times from worst-case phase
with good Running Disparity
(RD)0000 FFD0.0 31.7
code received with good RD
K28.1 (ESCON Connect_SOF)0
K28.5 (ESCON Passive_SOF) 0
RD was +
RD was
with wrong RD
sured while receiving data carried by a bandwidth-limited chan-
nel (e.g., a coaxial transmission line) while maintaining a Bit Error
Rate (BER) <10
while receiving data carried by a random-noise-limited channel
(e.g., a fiber-optic transmission system with low light levels) while
maintaining a Bit Error Rate (BER) <10
or frequency change in the serial input data stream, to re-
ceiving data within BER objective of 10
supplies within specifications, stable REFCLK input frequency
and normal data framing protocols are assumed. Note: Acqui-
sition time is measured from worst-case phase or frequency
change to zero phase and frequency error. As a result of the
receiver’s wide jitter tolerance, valid data will appear at the receiv-
er’s outputs a few byte times after a worst-case phase change.
12
.
j
) > 90% of t
RVS SC/D Qouts Name
B
1
1
1
1
0
j
. Total of D
) >40% of t
1
1
1
1
1
1
1
12
B
. Typically measured
.
12
00 0B C0.0 11.0
27
47
E0
E1
E2
E4
. Stable power
j
B
+ R
CY7B923
CY7B933
. Typically mea-
j
.
C7.1
C7.2
C0.7
C1.7
C2.7
C4.7