CY7B923-400JI CYPRESS [Cypress Semiconductor], CY7B923-400JI Datasheet - Page 15

• Manufacturer Part Number: CY7B923-400JI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Bypass Mode Operation
In Bypass mode the input data is interpreted as ten (10) bits
(D
be serialized and sent over the link. This data can use any encoding
method suitable to the designer. The only restrictions upon the data
encoding method is that it contain suitable transition density for the
Receiver PLL data synchronizer (one per 10 bit byte), and that it be
compatible with the transmission media.
Data loaded into the Input register on the rising edge of CKW
will be loaded into the Shifter on the subsequent rising edges
of CKW. It will then be shifted to the outputs one bit at a time
using the internal clock generated by the clock generator. The
first bit of the transmission character (Da) will appear at the output
(OUTA , OUTB , and OUTC ) after the next CKW edge.
While in either the Encoded mode or Bypass mode, if a CKW
edge arrives when the inputs are not enabled (ENA and ENN
both HIGH), the Encoder will insert a pad character K28.5 (e.g., C5.0)
b-h
), SC/D (Da), and SVS (Dj) of pre-encoded transmission data to
ENA
CKR
HOTLINK TRANSMIT TER
ASYNCHRONOUS FIFO
ASYNCHRONOUS FIFO
CKW
HOTLINK RECEIVER
RDY
7C42X/3X/6X/7X
7C42X/3X/6X/7X
W
7B923
7B933
RP
R
Q
D
Figure 5. Seamless FIFO Interface
0
0
Q
D
0
0
7
7
,SC/D
,SC/D
9
9
8
8
15
to maintain proper link synchronization (in Bypass mode the proper
sense of running disparity cannot be guaranteed for the first pad char-
acter, but is correct for all pad characters that follow). This automatic
insertion of pad characters can be inhibited by insuring that the Trans-
mitter is always enabled (i.e., ENA or ENN is hard-wired LOW).
PECL Output Functional and Connection Options
The three pairs of PECL outputs all contain the same informa-
tion and are intended for use in systems with multiple connec-
tions. Each output pair may be connected to a different serial
media, each of which may be a different length, link type, or
interface technology. For systems that do not require all three
output pairs, the unused pairs should be wired to V
mize the power dissipated by the output circuit, and to minimize un-
wanted noise generation. An internal voltage comparator detects
when an output differential pair is wired to V
source for that pair to be disabled. This results in a power savings of
around 5 mA for each unused pair.
ENR
ENN
CKR
CKW
HOTLINK TRANSMIT TER
HOTLINK RECEIVER
CKW
CKR
CLOCKED FIFO
CLOCKED FIFO
RDY
ENW
7C44X/5X
7C44X/5X
7B923
7B933
Q
D
0
0
Q
D
0
0
7
7
,SC/D
,SC/D
9
CC
8
8
9
, causing the current
CY7B923
CY7B933
B923–21
CC
to mini-