ICS1893CK ICST [Integrated Circuit Systems], ICS1893CK Datasheet - Page 25

• Manufacturer Part Number: ICS1893CK
• Description: 3.3-V 10Base-T/100Base-TX Integrated PHYceive
• Manufacturer: ICST [Integrated Circuit Systems]

6.1 Functional Block: Media Independent Interface
ICS1893CF, Rev. F, 03/01/07
All ICS1893CF MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the
ICS1893CF MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz
(for 10Base-T operations).
The Media Independent Interface (MII) consists of two primary components:
1. An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893CF).
2. An interface between the PHY (the ICS1893CF) and an STA (Station Management entity). The
The ICS1893CF Management Register set (discussed in
of the following:
•
•
•
Basic Management registers.
As defined in the ISO/IEC 8802-3 standard, these registers include the following:
Extended Management registers.
As defined in the ISO/IEC 8802-3 standard, the ICS1893CF supports Extended registers that provide
access to the Organizationally Unique Identifier and all auto-negotiation functionality.
ICS (Vendor-Specific) Management registers.
The ICS1893CF provides vendor-specific registers for enhanced PHY operations. Among these is the
QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY
information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with a
single register access.
– Control Register (register 0), which handles basic device configuration
– Status Register (register 1), which reports basic device capabilities and status
ICS1893CF Data Sheet Rev. F - Release
This MAC-PHY part of the MII consists of three subcomponents:
a. A synchronous Transmit interface that includes the following signals:
b. A synchronous Receive interface that includes the followings signals:
c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision
STA-PHY part of the MII is a two-wire, Serial Management Interface that consists of the following:
a. A clock (MDC)
b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the
Detection signal (COL).
ICS1893CF Management Register set
(1) A data nibble, TXD[3:0]
(2) A delimiter, TXEN
(3) A clock, TXCLK
(1) A data nibble, RXD[3:0]
(2) An error indicator, RXER
(3) A delimiter, RXDV
(4) A clock, RXCLK
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
25
Chapter 7, “Management Register
Chapter 6 Functional Blocks
Set”) consists
Mar. 2007