CY7C135 CYPRESS [Cypress Semiconductor], CY7C135 Datasheet - Page 8

• Manufacturer Part Number: CY7C135
• Description: 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes:
Document #: 38-06038 Rev. *B
Semaphore Read After Write Timing, Either Side (CY7C1342 only)
23. I/O
24. Semaphores are reset (available to both ports) at cycle start.
25. If t
22. CE = HIGH for the duration of the above timing (both write and read cycle).
Timing Diagram of Semaphore Contention (CY7C1342 only)
A 0R –A 2R
A 0L –A 2L
SPS
A
0R
0
SEM
–A
SEM R
R/W
SEM L
I/O
= I/O
R/W R
R/W L
is violated, it is guaranteed that only one side will gain access to the semaphore.
OE
2
0
0L
= LOW (request semaphore); CE
t
SA
(continued)
VALID ADDRESS
t
R
AW
= CE
WRITE CYCLE
t
t
PWE
SCE
L
t
= HIGH.
SD
DATA
t SPS
MATCH
MATCH
t
IN
HA
VALID
t
HD
t
SWRD
[23,24,25]
t
SOP
[22]
t
SOP
READ CYCLE
VALID ADDRESS
t
AA
t
DOE
t
ACE
DATA
OUT
VALID
CY7C1342
t
OHA
CY7C135
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