CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet - Page 13

• Manufacturer Part Number: CY7C1354A
• Description: 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05161 Rev. *B
TAP Electrical Characteristics
V
V
IL
IL
IL
V
V
V
V
Notes:
Parameter
22. X = 69 for the x36 configuration;
23. All voltage referenced to V
24. Overshoot: V
25. This parameter is sampled.
TDI
IH
Il
OLC
OHC
OLT
OHT
I
I
O
X = 50 for the x18 configuration.
t < 200 ms. During normal operation, V
t
KHKL
TDI
TDI
(min.).
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
TMS and TDI Input Leakage Current
Output Leakage Current
LVCMOS Output Low Voltage
LVCMOS Output High Voltage
LVTTL Output Low Voltage
LVTTL Output High Voltage
IH
(AC) < V
Selection
Circuitry
CC
SS
Description
1.5V for t < t
(GND).
CCQ
KHKH
must not exceed V
(20°C < T
/2; undershoot: V
[23]
[23, 24]
[23]
Figure 2. TAP Controller Block Diagram
[23, 24]
31
x
[23, 25]
[23, 25]
30
Identification Register
.
j
TAP Controller
< 110°C; V
Instruction Register
29
.
0V < V
0V < V
Output disabled,
0V < V
I
I
I
I
CC
OLC
OHC
OLT
OHT
IL
Boundary Scan Register
(AC) <–0.5V for t < t
. Control input signals (such as WEN and ADV/LD) may not have pulse widths less than
= 8.0 mA
= 100 A
= 8.0 mA
= 100 A
Test Conditions
.
.
IN
IN
IN
CC
Bypass Register
< V
< V
< V
.
.
= 3.3V –0.2V and +0.3V unless otherwise noted)
CC
CC
CCQ
2
2
2
KHKH
1
1
1
/2; power-up: V
0
0
0
0
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
[22]
V
IH
CC
< 3.6V and V
Min.
–0.3
–5.0
–5.0
–30
2.0
2.4
– 0.2
Selection
Circuitry
CC
< 3.135V and V
V
CC
Max.
0.8
5.0
5.0
0.2
0.4
30
+ 0.3
Page 13 of 31
CCQ
< 1.4V for
TDO
Unit
V
V
V
V
V
V
A
A
A