CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet - Page 22

• Manufacturer Part Number: CY7C1354A
• Description: 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05161 Rev. *B
Switching Waveforms
Write Timing
Notes:
44. D(A
45. Individual Byte Write signals (BWx) must be valid on all Write and burst-Write cycles. A Write cycle is initiated when WEN signal is sampled LOW when ADV/LD
BWa#, BWb#
in the burst sequence of the base address A
the MODE input.
is sampled LOW. The byte Write information comes in one cycle before the actual data is presented to the SRAM.
BWa, BWb,
BWc, BWd
ADDRESS
ADV/LD#
ADV/LD
1
) represents the first input to the external address A1. D(A
WEN
CKE#
R/W#
CEN
CLK
CE
CE#
OE#
OE
DQ
[40, 41, 42, 43, 44, 45]
BW(A
A
1
1
)
t
t
t
t
t
t
S
S
S
S
S
S
Pipeline Write
(continued)
BW(A
A
2
2
)
t
SD
2
, etc., where address bits A0 and A1 are advancing for the four-word burst in the sequence defined by the state of
t
t
t
t
t
t
H
H
H
H
H
H
Pipeline Write
BW(A
D(A
2
+1)
1
)
t
HD
t
KC
2
) represents the first input to the external address A
t
KL
BW(A
D(A
2
+2)
2
)
BW(A
D(A
2
2
+3)
+1)
t
KH
(CKE# HIGH , eliminates
current L-H clock edge)
Burst Pipeline Write
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
BW(A
2
D(A
; D(A
2
+2)
2
)
2
+ 1) represents the next input data
D(A
2
(Burst Wraps around
+3)
to initial state)
Page 22 of 31
D(A
2
)