CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet - Page 21
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CY7C1354A
Manufacturer Part Number
CY7C1354A
Description
256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY7C1354A.pdf
(31 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1354A-133AC
Manufacturer:
CYP
Quantity:
20 000
Document #: 38-05161 Rev. *B
Switching Waveforms
Read Timing
Notes:
39. Q(A
40. CE
41. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
42. WEN is “Don’t Care” when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the WEN signal
43. BWc and BWd apply to 256K × 36 device only.
BWa#, BWb#
BWa, BWb,
BWc, BWd
data in the burst sequence of the base address A
state of the MODE input.
inverted to the CE signal. For example, when CE is LOW on this waveform, CE
when new address and control are loaded into the SRAM.
ADDRESS
ADV/LD#
3
ADV/LD
1
timing transitions are identical to the CE signal. For example, when CE is LOW on this waveform, CE
) represents the first output from the external address A
CKE#
R/W#
WEN
CEN
CLK
CE#
OE#
CE
OE
DQ
[39, 40, 41, 42, 43]
A
1
t
t
t
t
t
S
S
S
S
S
t
KQLZ
Pipeline Read
A
2
t
t
t
t
t
H
H
H
H
H
Pipeline Read
Q(A
2
, etc., where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the
1
)
t
KQ
1
t
. Q(A
KC
Q(A
t
KL
2
2
) represents the first output from the external address A
)
t
KQX
Q(A
2
is HIGH.
2
+1)
t
KH
BURST PIPELINE READ
(CKE# HIGH , eliminates
current L-H clock edge)
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Q(A
2
+2)
3
is LOW. CE
2
2
timing transitions are identical but
; Q(A
Q(A
2
+1) represents the next output
(Burst Wraps around
2
+3)
to initial state)
Page 21 of 31
Q(A
2
)
t
KQHZ