CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet - Page 16

• Manufacturer Part Number: CY7C1354A
• Description: 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05161 Rev. *B
Instruction Codes
EXTEST
IDCODE
SAMPLE-Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Code
000
001
010
100
101
011
110
111
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
Do not use these instructions; they are reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Places the bypass register between TDI and TDO. This instruction does
not affect device operations.
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Description
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