CY7C1355C-100BZC CYPRESS [Cypress Semiconductor], CY7C1355C-100BZC Datasheet - Page 4

• Manufacturer Part Number: CY7C1355C-100BZC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05688 Rev. *D
Pin Definitions
OE
CEN
ZZ
DQ
Mode
V
V
DD
DDQ
Name
s
4,11,20,27,54,
52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,
18,19,22,23,
24,25,28,29
15,41,65,91
8,9,12,13,
61,70,77
2,3,6,7,
TQFP
(continued)
86
87
64
31
G4,G8,H2,
G1,D2,E2,
C3,C9,D3,
L9,M3,M9,
D1,E1,F1,
K1,L1,M1,
D4,D8,E4,
D9,E3,E9,
F3,F9,G3,
F2,G2,J1,
E8,F4,F8,
H4,H8,J4,
L4,L8,M4,
K3,K9,L3,
J8,K4,K8,
G9,J3,J9,
L10,M10,
D10,E10,
F10,G10,
M11,L11,
D11,E11,
F11,G11,
J10,K10,
J2,K2,L2
K11,J11,
FBGA
N3,N9
H11
M2
M8
B8
A7
R1
Asynchronous
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
I/O Power
Strap Pin
Supply
Input-
Input-
Input-
Input
I/O-
I/O
Output Enable, asynchronous input, active LOW. Combined
with the synchronous logic block inside the device to control the
direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the
data portion of a write sequence, during the first clock when
emerging from a deselected state, when the device has been
deselected.
Clock Enable Input, active LOW. When asserted LOW the
Clock signal is recognized by the SRAM. When deasserted
HIGH the Clock signal is masked. Since deasserting CEN does
not deselect the device, CEN can be used to extend the previous
cycle when required.
ZZ “sleep” Input. This active HIGH input places the device in a
non-time critical “sleep” condition with data integrity preserved.
For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
Bidirectional Data I/O Lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge of CLK.
As outputs, they deliver the data contained in the memory
location specified by address during the clock rise of the Read
cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can
behave as outputs. When HIGH, DQ
condition. The outputs are automatically tri-stated during the
data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
Mode Input. Selects the burst order of the device.
When tied to GND selects linear burst sequence. When tied to
V
Power supply for the I/O circuitry.
DD
or left floating selects interleaved burst sequence.
Description
s
are placed in a tri-state
CY7C1379C
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