M29W040-100K1R STMICROELECTRONICS [STMicroelectronics], M29W040-100K1R Datasheet - Page 10

• Manufacturer Part Number: M29W040-100K1R
• Description: 4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29W040
Table 12A. Read AC Characteristics
(T
Notes: 1. Sampled only, not 100% tested.
Toggle bit (DQ6). When Programming operations
are in progress, successive attempts to read DQ6
will output complementary data. DQ6 will toggle
following toggling of either G or E when G is low.
The operation is completed when two successive
reads yield the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing. The toggle bit is valid only effective during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the byte to be programmed belongs to a
protected block the command will be ignored. If the
blocks selected for erasure are protected, DQ6 will
toggle for about 100 s and then return back to
Read. See Figure 11 for Toggle Bit flowchart and
Figure 12 for Toggle Bit waveforms.
Error bit (DQ5). This bit is set to ’1’ by the P/E.C
when there is a failure of byte programming, block
erase, or chip erase that results in invalid data
being programmedin the memory block. In case of
error in block erase or byte program, the block in
which the error occured or to which the pro-
10/31
Symbol
t
t
t
t
t
t
GHQZ
A
GLQX
GLQV
EHQZ
ELQX
ELQV
t
t
t
t
t
GHQX
AVQV
EHQX
AXQX
AVAV
= 0 to 70 C, –20 to 85 C or –40 to 85 C)
2. G may be delayed by up to t
(1)
(2)
(1)
(2)
(1)
(1)
t
t
Alt
t
ACC
t
t
t
t
t
t
OLZ
t
t
OH
OH
OH
RC
CE
OE
HZ
DF
LZ
Address Valid to Next Address Valid
Address Valid to Output Valid
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output
Transition
Output Enable Low to Output Valid
Chip Enable High to Output
Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output
Transition
Output Enable High to Output Hi-Z
Address Transition to Output
Transition
Parameter
ELQV
- t
GLQV
after the falling edge of E without increasing t
Test Condition
E = V
E = V
E = V
grammed byte belongs, must be discarded. Other
blocks may still be used. Error bit resetsafter Reset
(RST) instruction. In case of success, the error bit
will set to ’0’ during Program or Erase and to valid
data after write operation is completed.
Erase Timer bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last Block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 80 to 120 s, DQ3 returns
back to ’1’.
Coded Cycles. The two coded cycles unlock the
Command Interface. They are followed by a com-
mand input or a comand confirmation. The coded
cycles consist of writing the data AAh at address
5555h during the first cycle and data 55hat address
2AAAh during the second cycle. Addresses are
latched on the falling edge of W or E while data is
latched on the rising edge of W or E. The coded
cycles happen on first and second cycles of the
command write or on the fourth and fifth cycles.
G = V
G = V
G = V
G = V
E = V
E = V
E = V
E = V
IL
IL
IL
, G = V
, G = V
, G = V
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
V
CC
Min
100
0
0
0
0
0
C
ELQV
= 3.3V 0.3V
L
-100
= 30pF
.
Max
100
100
40
20
20
M29W040
V
CC
Min
120
0
0
0
0
0
= 3.3V 0.3V
-120
Max
120
120
50
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns