M29W040-100K1R STMICROELECTRONICS [STMicroelectronics], M29W040-100K1R Datasheet - Page 8

• Manufacturer Part Number: M29W040-100K1R
• Description: 4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29W040
Instructions and Commands
The Command Interface (C.I.) latches commands
written to the memory. Instructions are made up
from one or more commands to perform Read
Array/Reset, Read Electronic Signature, Power
Down, Block Erase, Chip Erase, Program, Block
Erase Suspend and Erase Resume. Commands
are made of address and data sequences. Ad-
dresses are latched on the falling edge of W or E
and data is latched on the rising of W or E. The
instructions require from 1 to 6 cycles, the first or
first three of which are always write operations
used to initiate the command. They are followed by
either further write cycles to confirm the first com-
mand or execute the command immediately. Com-
mand sequencing must be followed exactly. Any
invalid combination of commands will reset the
device to Read Array. The increased number of
cycles has been chosen to assure maximum data
security. Commands are initialised by two preced-
ing coded cycles which unlock the Command Inter-
face. In addition, for Erase, command confirmation
is again preceeded by the two coded cycles.
P/E.C. status is indicated during command execu-
tion by Data Polling on DQ7, detectionof Toggle on
8/31
Table 8. Status Register
Note: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
DQ
7
6
5
4
3
2
1
0
Data
Polling
Toggle Bit
Error Bit
Erase
Time Bit
Reserved
Reserved
Reserved
Name
’-1-0-1-0-1-0-1-’
’-0-0-0-0-0-0-0-’
’-1-1-1-1-1-1-1-’
Logic Level
DQ
DQ
’1’
’0’
’1’
’0’
’1’
’0’
’1’
’0’
Erase Complete
Erase on going
Program Complete
Program on going
Erase or Program on going
Program (’0’ on DQ6)
Complete
Erase or Program
(’1’ on DQ6) Complete
Program or Erase Error
Program or Erase on going
Erase Timeout Period Expired
Erase Timeout Period on
going
Definition
DQ6, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand executionwill automaticallyoutput those four
bits. The P/E.C. automatically sets bits DQ3, DQ5,
DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and
DQ4) are reserved for future use and should be
masked.
Data Polling bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation,DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid only effective during P/E.C. operation, that is
after the fourth W pulse for programming or after
the sixth W pulse for Erase. It must be performed
at the address being programmed or at an address
within the block being erased. If the byte to be
programmed belongs to a protectedblock the com-
mand is ignored. If all the blocks selected for era-
sure are protected, DQ7 will set to ’0’ for about
100 s, and then return to previous addressed
memory data. See Figure 9 for the Data Polling
flowchart and Figure 10 for the Data Polling wave-
forms.
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Successive read output complementary
data on DQ6 while Programming or Erase
operations are going on. DQ6 remain at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
This bit is set to ’1’ if P/E.C. has exceded
the specified time limits.
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES). An additional block to be erased in
parallel can be entered to the P/E.C.
Note