CY7C1382D CYPRESS [Cypress Semiconductor], CY7C1382D Datasheet
CY7C1382D
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CY7C1382D Summary of contents
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... Synchronous self-timed write ■ Asynchronous output enable ■ Single cycle chip deselect ■ CY7C1380D/CY7C1382D is available in JEDEC-standard ■ Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FPBGA package; CY7C1380F/CY7C1382F is available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 119-ball BGA and 165-ball FPBGA package IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ...
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... BW B WRITE REGISTER DQ DQP BYTE A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL Logic Block Diagram – CY7C1382D/CY7C1382F ADDRESS A0, A1, A REGISTER ADV BURST CLK COUNTER AND LOGIC ADSC DQ DQP B, B WRITE REGISTER DQP WRITE REGISTER A BWE ...
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... TAP Instruction Set ................................................... 14 Reserved ................................................................... 15 TAP Timing ...................................................................... 15 TAP AC Switching Characteristics ............................... 15 3.3 V TAP AC Test Conditions ....................................... 16 2.5 V TAP AC Test Conditions ....................................... 16 Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F TAP DC Electrical Characteristics and Operating Conditions ..................................................... 16 Identification Register Definitions ................................ 17 Scan Register Sizes ....................................................... 17 Identification Codes ....................................................... 17 119-ball BGA Boundary Scan Order ............................ 18 165-ball BGA Boundary Scan Order ...
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... Pin Configurations 100-pin TQFP Pinout (3-Chip Enable) Figure 1. CY7C1380D, CY7C1380F (512 K × 36) Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Figure 2. CY7C1382D, CY7C1382F (1 M × 18) Page [+] Feedback ...
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... BWE DQP MODE NC/36M A TMS TDI TCK TDO CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F DDQ A NC/576M A NC/1G DQP DDQ DDQ DQ ...
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... TDO TDI TCK TMS Figure 6. CY7C1382D/CY7C1382F (1 M × 18 BWE CLK ...
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... CE to select or deselect the device select or deselect the device sampled only when a new external address deasserted HIGH. 1 are placed in a tri-state condition. X CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F [4] , and CE are sampled active. A1 and BWE HIGH sampled ...
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... No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Document Number: 38-05543 Rev This pin is not available on TQFP packages. SS CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F or left DD . This pin is not available This pin is not available on ...
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... Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a common I/O device, the output enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so tri-states the output drivers safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE ...
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... Device operation to ZZ ZZS t ZZ recovery time ZZREC t ZZ Active to sleep current ZZI t ZZ Inactive to exit sleep current RZZI Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Table 2. Interleaved Burst Address Table (MODE = Floating or VDD) First Second Address Address A1 ...
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... CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F ADV WRITE OE CLK L–H Tri-state L–H Tri-state L–H Tri-state L–H Tri-state L–H Tri-state ...
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... B B Write Bytes B, A Write All Bytes Write All Bytes Notes 10 Don't Care Logic HIGH Logic LOW. 11. Table only lists a partial listing of the byte write combinations. Any combination of BW Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F GW BWE ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380D/CY7C1382D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3 2.5 V I/O logic levels. The CY7C1380D/CY7C1382D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register ...
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... It also places the instruction register between the TDI and TDO balls and enables Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. ...
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... These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOV t TDOX DON’T CARE UNDEFINED Description / ns CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Min Max Unit 50 – ns – 20 MHz 20 – – ns – 10 ...
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... DDQ V = 2.5 V DDQ I = 100 µ 3 DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ GND < V < DDQ CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F to 2 1.25V 50Ω TDO Ω 20pF O Min Max Unit 2.4 – V 2.0 – V 2.9 – V 2.1 – V – 0.4 V – ...
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... Bit Size (×36 Description CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Description Describes the version number. Reserved for internal use. Defines the memory type and architecture. Defines the memory type and architecture. Defines the width and density. Allows unique identification of SRAM vendor ...
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... Notes 16. Balls which are NC (No Connect) are pre-set LOW. 17. Bit pre-set HIGH. Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D [16, 17] Ball ID Bit # Ball ...
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... CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Bit # Ball ...
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... /2), undershoot: V (AC) > –2 V (pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F + 0 Ambient DDQ Temperature 0 °C to +70 °C 3.3 V–5%/+10% 2.5 V – Min Max 3.135 3 ...
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... DDQ GND 351 INCLUDING JIG AND (b) SCOPE R = 1667 2 DDQ GND 1538 INCLUDING JIG AND SCOPE (b) CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 119 BGA 165 FBGA Unit Package Package 119 BGA 165 FBGA Unit ...
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... V “AC Test Loads and Waveforms” and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 200 MHz 167 MHz Unit Max Min Max 1 – ...
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... CO t OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH LOW. X CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3 Extended BURST WRITE is HIGH LOW HIGH ...
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... WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs is HIGH LOW HIGH Page [+] Feedback ...
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... DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05543 Rev. *I [35, 36] Figure 13. ZZ Mode Timing ZZI I DDZZ High-Z DON’T CARE “Truth Table” on page 11 for all possible signal conditions to deselect the device. CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...
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... Die Revision 90nm errata fix PCN084636 Part Identifier: 138X = 1380 or 1382 1380 = SCD, 512 K × 36 (18 Mb) 1382 = SCD × 18 (18 Mb) Marketing Code SRAM Company ID Cypress CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Operating Range Commercial Commercial Commercial Industrial ...
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... Package Diagrams Figure 14. 100-pin Thin Plastic Quad Flat Pack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 51-85050 *D Page [+] Feedback ...
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... Package Diagrams (continued) Figure 15. 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 51-85115 *C Page [+] Feedback ...
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... Package Diagrams (continued) Figure 16. 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180 Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 51-85180 *C Page [+] Feedback ...
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... TDI test data-in TDO test data-out TQFP thin quad flat pack WE write enable TTL transistor–transistor logic Document Number: 38-05543 Rev. *I CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes ...
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... Document History Page Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Document Number: 38-05543 Submission Orig. of REV. ECN NO. Date Change ** 254515 See ECN RKF *A 288531 See ECN SYT *B 326078 See ECN PCI *C 416321 See ECN NXR *D 475009 See ECN VKN ...
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... Document History Page Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Document Number: 38-05543 Submission Orig. of REV. ECN NO. Date Change *I 3159479 02/01/2011 NJY Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...