CY7C1382D CYPRESS [Cypress Semiconductor], CY7C1382D Datasheet - Page 10

• Manufacturer Part Number: CY7C1382D
• Manufacturer: CYPRESS [Cypress Semiconductor]

Burst Sequences
The
provides a two-bit wraparound counter, fed by A1: A0, that
implements an interleaved or a linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE
ADSP, and ADSC must remain inactive for the duration of t
after the ZZ input returns LOW.
Table 4. ZZ Mode Electrical Characteristics
Document Number: 38-05543 Rev. *I
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Description
1
, CE
2
, CE
ZZREC
3
,
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Table 2. Interleaved Burst Address Table (MODE = Floating
or VDD)
Table 3. Linear Burst Address Table (MODE = GND)
Test Conditions
DD
DD
Address
Address
A1: A0
A1: A0
– 0.2 V
– 0.2 V
First
First
00
01
10
00
01
10
11
11
Address
Address
Second
Second
A1: A0
A1: A0
CY7C1380D, CY7C1382D
01
00
11
10
01
10
11
00
CY7C1380F, CY7C1382F
2t
Min
CYC
–
–
–
0
Address
Address
A1: A0
A1: A0
Third
Third
10
00
01
10
00
01
11
11
2t
2t
Max
80
CYC
CYC
–
–
Address
Address
Page 10 of 33
Fourth
A1: A0
Fourth
A1: A0
Unit
mA
ns
ns
ns
ns
11
10
01
00
11
00
01
10
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