CY7C1382D CYPRESS [Cypress Semiconductor], CY7C1382D Datasheet - Page 15

• Manufacturer Part Number: CY7C1382D
• Manufacturer: CYPRESS [Cypress Semiconductor]

when the EXTEST is entered as the current instruction. When
HIGH, it enables the output buffers to drive the output bus. When
LOW, this bit places the output bus into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 38-05543 Rev. *I
Notes
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
12. t
13. Test conditions are specified using the load in TAP AC test conditions. t
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
[12, 13]
Description
t TMSS
t TDIS
t TMSH
t TDIH
t TH
DON’T CARE
R
t
TL
/t
F
= 1 ns.
t CYC
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
UNDEFINED
t TDOX
t TDOV
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Min
50
20
20
–
–
0
5
5
5
5
5
5
Max
20
10
–
–
–
–
–
–
–
–
–
–
Page 15 of 33
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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