CY7C1382D CYPRESS [Cypress Semiconductor], CY7C1382D Datasheet - Page 24

• Manufacturer Part Number: CY7C1382D
• Manufacturer: CYPRESS [Cypress Semiconductor]

ata Out (Q)
Switching Waveforms
Document Number: 38-05543 Rev. *I
Data In (D)
Notes
ADDRESS
30. On this diagram, when CE is LOW: CE
31. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
ADSC
ADSP
BWE,
ADV
BW
CLK
GW
OE
CE
X
BURST READ
High-Z
t ADS
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t CL
t DS
Single WRITE
D(A1)
t ADH
t DH
(continued)
1
is LOW, CE
A2
Figure 11. Write Cycle Timing
2
is HIGH and CE
D(A2)
DON’T CARE
D(A2 + 1)
t WES
3
BURST WRITE
is LOW. When CE is HIGH: CE
t WEH
D(A2 + 1)
UNDEFINED
ADV suspends burst
X
LOW.
D(A2 + 2)
[30, 31]
ADSC extends burst
1
is HIGH or CE
D(A2 + 3)
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
t ADS
A3
2
D(A3)
is LOW or CE
t ADH
t
ADVS
t WES
Extended BURST WRITE
D(A3 + 1)
t WEH
t
ADVH
3
is HIGH.
D(A3 + 2)
Page 24 of 33
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