AD9518-0A-PCBZ AD [Analog Devices], AD9518-0A-PCBZ Datasheet - Page 6

• Manufacturer Part Number: AD9518-0A-PCBZ
• Description: 6-Output Clock Generator
• Manufacturer: AD [Analog Devices]

AD9518-0
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
1
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL
PROPAGATION DELAY, t
OUTPUT SKEW, LVPECL OUTPUTS
1
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Input Frequency
Input Sensitivity, Differential
Input Common-Mode Range, V
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Output Rise Time, t
Output Fall Time, t
CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution
Clock Distribution Configuration
Variation with Temperature
LVPECL Outputs That Share the
LVPECL Outputs on Different
Dividers
All LVPECL Outputs Across Multiple
Parts
Input Level, Differential
Input Common-Mode Voltage, V
Output Frequency, Maximum
Output High Voltage (V
Output Low Voltage (V
Output Differential Voltage (V
Configuration
Same Divider
FP
RP
PECL
OL
OH
,
)
)
OD
)
1
CMR
CM
Min
0
0
1.3
1.3
3.9
Min
2950
V
1.12
V
2.03
550
Min
835
773
1
1
S_LVPECL
S_LVPECL
−
−
Typ
150
1.57
150
4.7
2
Typ
V
0.98
V
1.77
790
Typ
70
70
995
933
0.8
5
13
S_LVPECL
S_LVPECL
−
−
Rev. C | Page 6 of 64
Max
2.4
1.6
2
1.8
1.8
5.7
Max
V
0.84
V
1.49
980
Max
180
180
1180
1090
15
40
220
S_LVPECL
S_LVPECL
−
−
CM
.
Unit
GHz
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
Unit
MHz
V
V
mV
Unit
ps
ps
ps
ps
ps/°C
ps
ps
ps
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Test Conditions/Comments
Termination = 50 Ω to V
Differential (OUT, OUT)
Using direct to output; see Figure 16 for peak-to-peak
differential amplitude
This is V
default amplitude setting with driver not toggling; the
peak-to-peak amplitude measured using a differential
probe across the differential pair with the driver toggling
is roughly 2× these values (see Figure 16 for variation
over frequency)
Test Conditions/Comments
Termination = 50 Ω to V
20% to 80%, measured differentially
80% to 20%, measured differentially
See Figure 28
See Figure 30
OH
− V
OL
for each leg of a differential pair for
S
− 2 V; level = 810 mV
S
− 2 V
Data Sheet