W83194R-58 WINBOND [Winbond], W83194R-58 Datasheet - Page 9

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W83194R-58

Manufacturer Part Number
W83194R-58
Description
100 MHZ AGP CLOCK FOR VIA CHIPSET
Manufacturer
WINBOND [Winbond]
Datasheet
8.3.2 Register 1: CPU, 48/24 MHz Clock Register (1 = Active, 0 = Inactive), continued
8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)
8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)
BIT
BIT
BIT
BIT
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
@POWERUP
@POWERUP
@POWERUP
@POWERUP
1
1
1
1
x
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x
x
PIN
PIN
PIN
PIN
40
41
43
44
15
14
12
11
10
28
29
31
32
34
35
37
38
7
8
-
-
-
CPUCLK3 (Active/Inactive)
CPUCLK2 (Active/Inactive)
CPUCLK1 (Active/Inactive)
CPUCLK0 (Active/Inactive)
Reserved
PCICLK_F (Active/Inactive)
AGP0 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLk1 (Active/Inactive)
PCICLK0 (Active/Inactive)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Reserved
Reserved
- 9 -
Preliminary W83194R-37/-58
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Publication Release Date: April 1999
Revision A1

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