CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet
CY7C64713
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CY7C64713 Summary of contents
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... Smart USB Engine “Soft Configuration” FIFO and endpoint memory Easy firmware changes (master or slave operation) Figure 1-1. Block Diagram • 3901 North First Street • CY7C64713/ controller, runs at 100 or 400 KHz Master Abundant I/O Additional I/Os (24) including two USARTS General ADDR (9) ...
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... Functional Description EZ-USB FX1 (CY7C64713/ full-speed highly integrated, USB microcontroller. By integrating the USB trans- ceiver, serial interface engine (SIE), enhanced 8051 microcon- troller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages. ...
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... USB specification. 4.8 Interrupt System 4.8.1 INT2 Interrupt Request and Enable Registers FX1 implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual (TRM) for more details. CY7C64713/ SCON1 PSW ACC B ...
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... EP8 OUT was Pinged and it NAK’d Bus errors exceeded the programmed limit reserved reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error CY7C64713/14 Notes Page ...
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... ISR Interrupt service routine. Note: If the external clock is powered at the same time as the CY7C64713/4 and has a stabilization wait period, it must be added to the 200 µ Document #: 38-08039 Rev. *B Source ...
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... USB upload • Setup data pointer 2 • interface boot load. 4.10.3 External Code Memory The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as data memory. CY7C64713/ 3. RESET Powered Reset Page ...
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... KBytes data memory RAM here—RD#/WR# Data strobes are not (RD#,WR#)* active) Data 2 C interface boot access Figure 4-4. External Code Memory CY7C64713/14 48 KBytes External Code Memory (PSEN#) (OK to populate program memory here— PSEN# strobe is not active) Code 64 KBytes ...
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... For an ISOCHRONOUS endpoint the maximum number of bytes it can accommodate is 1023. For endpoint configuration options, see Figure 4-5. 4.12.3 Setup Data Buffer A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup data from a CONTROL transfer. CY7C64713/14 Page ...
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... Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between 2 3 “USB FIFOS” and “Slave FIFOS.” Since they are physically the same memory, no bytes are actually transferred between 64 buffers. 64 int 64 int 64 iso in (2×) CY7C64713/ ...
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... GPIF The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C64713/4 to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia. The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY) ...
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... WR#, are present in the 100-pin version. In the 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC. CY7C64713/ Interface Boot Load Access 2 C interface boot loader will load the 2 C interface boot loads only occur after 2 I ...
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... PE1/T1OUT PE0/T0OUT WR# CS OE# D5 PSEN A15 D2 A14 D1 A13 D0 A12 A11 A10 128 Figure 5-1. Signals CY7C64713/14 Slave FIFO FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] SLRD SLWR FLAGA FLAGB FLAGC INT0#/ PA0 INT1#/ PA1 SLOE WU2/PA3 FIFOADR0 FIFOADR1 PKTEND PA7/FLAGD/SLCS# Page ...
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... VCC 27 GND 28 INT4 *IFCLK 33 RESERVED BKPT SCL 36 SDA 37 OE# 38 Figure 5-2. CY7C64713/4 128-pin TQFP Pin Assignment Document #: 38-08039 Rev. *B CY7C64713/4 128-pin TQFP * denotes programmable polarity CY7C64713/14 102 PD0/FD8 101 *WAKEUP 100 VCC 99 RESET# 98 CTL5 ...
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... AGND 19 VCC 20 GND 21 INT4 *IFCLK 26 RESERVED 27 BKPT 28 SCL 29 SDA 30 Figure 5-3. CY7C64713/4 100-pin TQFP Pin Assignment Document #: 38-08039 Rev. *B PA7/*FLAGD/SLCS# CY7C64713/4 100-pin TQFP * denotes programmable polarity CY7C64713/14 PD0/FD8 80 *WAKEUP 79 VCC 78 RESET# 77 CTL5 76 GND 75 74 PA6/*PKTEND 73 PA5/FIFOADR1 72 PA4/FIFOADR0 ...
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... XTALOUT 4 XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 *IFCLK/**PE0/T0OUT 13 RESERVED 14 Figure 5-4. CY7C64713/4 56-pin QFN Pin Assignment Document #: 38-08039 Rev. *B CY7C64713/4 56-pin QFN * denotes programmable polarity CY7C64713/14 RESET# 42 GND 41 PA7/*FLAGD/SLCS# 40 PA6/*PKTEND 39 PA5/FIFOADR1 38 PA4/FIFOADR0 37 PA3/*WU2 36 PA2/*SLOE 35 PA1/INT1# ...
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... CY7C64713/4 Pin Definitions [8] Table 5-1. FX1 Pin Definitions 128 100 56 TQFP TQFP QFN Name Type AVCC Power AVCC Power AGND Ground AGND Ground DMINUS I/O DPLUS I/O Output 95 A1 Output 96 A2 Output 97 A3 Output 117 A4 Output 118 ...
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... FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0]. I Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits. (PA6) PA6 is a bidirectional I/O port pin. PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is programmable via FIFOPINPOLAR.5. CY7C64713/14 Description Page ...
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... GPIFADR2 is a GPIF address output pin. I Multiplexed pin whose function is selected by PORTCCFG.3 (PC3) PC3 is a bidirectional I/O port pin. GPIFADR3 is a GPIF address output pin. I Multiplexed pin whose function is selected by PORTCCFG.4 (PC4) PC4 is a bidirectional I/O port pin. GPIFADR4 is a GPIF address output pin. CY7C64713/14 Description Page ...
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... I Multiplexed pin whose function is selected by the PORTECFG.2 bit. (PE2) PE2 is a bidirectional I/O port pin. T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows. CY7C64713/14 Description Page ...
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... CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. H CTL3 is a GPIF control output. H CTL4 is a GPIF control output. H CTL5 is a GPIF control output. CY7C64713/14 Description Page ...
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... VCC. Connect to 3.3V power source. N/A VCC. Connect to 3.3V power source. N/A VCC. Connect to 3.3V power source. N/A VCC. Connect to 3.3V power source. N/A VCC. Connect to 3.3V power source. N/A VCC. Connect to 3.3V power source. N/A VCC. Connect to 3.3V power source. N/A VCC. Connect to 3.3V power source. N/A VCC. Connect to 3.3V power source. CY7C64713/14 Description Page ...
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... Ground N N N/A Document #: 38-08039 Rev. *B [8] Default N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A No Connect. This pin must be left open. N/A No Connect. This pin must be left open. N/A No-connect. This pin must be left open. CY7C64713/14 Description Page ...
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... LINE15 LINE14 LINE13 LINE12 LINE7 LINE6 LINE5 LINE4 COL5 COL4 COL3 COL2 LINE15 LINE14 LINE13 LINE12 LINE7 LINE6 LINE5 LINE4 CY7C64713/ Default xxxxxxxx RW CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA3 FLAGA2 ...
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... EP8 EP6 CY7C64713/ Default COL1 COL0 0 0 11111111 IN: PKTS[0] 0 PFC9 PFC8 10001000 bbbbbrbb OUT:PFC10 PFC9 IN:PKTS[2] 10001000 bbbbbrbb OUT:PFC8 PFC3 PFC2 PFC1 PFC0 00000000 RW IN: PKTS[0] 0 ...
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... BC6 BC5 BC4 0 BC6 BC5 BC4 BC6 BC5 BC4 BC6 BC5 BC4 BC6 BC5 BC4 CY7C64713/ Default EP4 EP2 EP1 EP0 00xxxxxx rrbbbbbb EP1 EP0 0 IBN 00000000 RW EP1 EP0 0 IBN xxxxxx0x bbbbbbrb SUSP SUTOK SOF ...
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... FSE LFUNC1 LFUNC0 TERMA2 TERMA1 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL5 CTL4 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL5 CTL4 HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD 0 CY7C64713/ Default 0 BC10 BC9 BC8 xxxxxxxx RW BC3 BC2 BC1 BC0 xxxxxxxx BC9 BC8 xxxxxxxx RW BC3 BC2 ...
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... DISCON CY7C64713/ Default 0 MSTB2 MSTB1 MSTB0 00100000 FALLING RISING 00000001 rrrrrrbb 00000010 RW TC27 TC26 TC25 TC24 00000000 RW TC19 TC18 TC17 TC16 00000000 RW ...
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... D4 1 PS1 PT2 PS0 DONE D15 D14 D13 D12 SM0_1 SM1_1 SM2_1 REN_1 CY7C64713/ Default 00000111 00000000 RW A11 A10 A9 A8 00000000 00000000 RW A11 A10 A9 A8 00000000 RW ...
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... D15 D14 D13 D12 RS1 1 ERESI RESI EX6 PX6 CY7C64713/ Default EXEN2 TR2 CT2 CPRL2 00000000 00000000 00000000 00000000 RW D11 D10 D9 D8 00000000 RW RS0 ...
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... Crystal Frequency) ... 24 MHz ± 100 ppm OSC .................................................................. Parallel Resonant Conditions 0< V < VCC OUT I = –4 mA OUT Except D+/D– D+/D– Connected Disconnected Connected Disconnected 8051 running, connected to USB VCC min = 3.0V CY7C64713/14 Min. Typ. Max. Unit 3.15 3.3 3.45 V µs 200 2 5.25 V –0.5 0 5.25 V –0.05 ...
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... ACC1 CL AV DSU t (48 MHz) = 3*t – t – ns. ACC1 CL AV DSU Document #: 38-08039 Rev STBH STBL [15 ACC1 data in Min 9.6 0 CY7C64713/ Typ. Max. Unit 20.83 ns 41.66 ns 83 Page Notes 48 MHz 24 MHz 12 MHz ...
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... CL AV DSU Document #: 38-08039 Rev. *B Stretch = STBH STBL t SCSL t SOEL t DSU [ ACC1 data in Stretch = 1 [16] t ACC1 Figure 10-2. Data Memory Read Timing Diagram Min. 9.6 0 CY7C64713/ DSU t DH data in Typ. Max. Unit 20.83 ns 41.66 ns 83 Page ...
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... Clock to CS Pulse LOW SCSL t Clock to Data Turn-on ON1 t Clock to Data Hold Time OFF1 Document #: 38-08039 Rev STBL STBH data out Stretch = 1 data out Figure 10-3. Data Memory Write Timing Diagram Description CY7C64713/ OFF1 Min. Max. Unit ...
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... Setup time when using internal 48-MHz IFCLK. x 19. IFCLK must not exceed 48 MHz. Document #: 38-08039 Rev IFCLK t SGA X t SRY t RYH valid t t SGD DAH X t XCTL N N+1 t XGD Description Description CY7C64713/14 [17] [18, 19] Min. Max. Unit 20. 6.7 ns [19] Min. Max. Unit 20.83 ...
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... SLOE Turn-off to FIFO Data Hold OEoff t Clock to FLAGS Output Propagation Delay XFLG t Clock to FIFO Data Output Propagation Delay XFD Document #: 38-08039 Rev IFCLK t RDH t SRD t XFLG N N OEon XFD Description Description CY7C64713/14 t OEoff [17] [19] Min. Max. Unit 20. 10.5 ns 10.5 ns 9.5 ns TBD 11 ns [19] Min. ...
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... SLRD to FIFO Data Output Propagation Delay XFD t SLOE Turn-on to FIFO Data Valid OEon t SLOE Turn-off to FIFO Data Hold OEoff Document #: 38-08039 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [20] Description CY7C64713/14 [17] Min. Max. Unit 10.5 ns 10.5 ns Page ...
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... Clock to FLAGS Output Propagation Time XFLG Note: 20. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08039 Rev IFCLK t WRH t SWR SFD FDH t XFLG Description Description CY7C64713/14 Z [17] [19] Min. Max. Unit 20. 9.5 ns [19] Min. ...
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... SPE t XFLG Description Description the FIFOs or thereafter. The only consideration is that the set- up time t and the hold time t SPE Although typically there are no specific timing requirements for asserting PKTEND in relation to SLWR, there exists a specific CY7C64713/14 [17] [20] Min. Max. Unit ...
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... FX2 failing to send the one byte/word short packet FDH SFD FDH SFD FDH SFD X-2 X-1 X-3 t PEpwl t XFLG Description CY7C64713/14 >= t WRH FDH SFD FDH FDH SFD 1 X Atleast one IFCLK cycle t PEpwh [17] [20] Min. Max. ...
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... Figure 10-13. Slave FIFO Address to Flags/Data Timing Diagram Table 10-16. Slave FIFO Address to Flags/Data Parameters Parameter t FIFOADR[1:0] to FLAGS Output Propagation Delay XFLG t FIFOADR[1:0] to FIFODATA Output Propagation Delay XFD Document #: 38-08039 Rev OEoff t OEon Description t XFLG t XFD N N+1 Description CY7C64713/14 [17] Min. Max. Unit 10.5 ns 10.5 ns [17] Min. Max. Unit 10.7 ns 14.3 ns Page ...
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... Figure 10-15. Slave FIFO Asynchronous Address Timing Diagram Table 10-18. Slave FIFO Asynchronous Address Parameters Parameter t FIFOADR[1:0] to RD/WR/PKTEND Setup Time SFA t RD/WR/PKTEND to FIFOADR[1:0] Hold Time FAH Document #: 38-08039 Rev SFA FAH [19] Description t SFA [20] Description CY7C64713/14 Min. Max. Unit 20.83 200 FAH [17] Min. Max. Unit ...
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... During the first read cycle, on the rising edge of the clock the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is asserted, the FIFO pointer is incre- mented and the next data value is placed on the data bus. CY7C64713/14 >= t RDH t t ...
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... PKTEND pin atleast one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet ( the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to section 10- 10 for further details on this timing. CY7C64713/14 t FAH >= t WRH ...
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... through 5. Note: In burst read mode, during SLOE is assertion, the data bus driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. CY7C64713/14 t FAH t t ...
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... WRpwh T=1 T=4 T=3 T SFD FDH SFD FDH N+1 N+2 T=2 T=5 SFA WRpwl before the de-asserting edge of SLWR. SFD from the de-asserting edge of SLWR. Package Type CY7C64713/14 t FAH t t WRpwl WRpwh T=7 T=9 t XFLG t t SFD FDH N+3 T PEpwl PEpwh [17 SLCS is used, it must also be asserted (SLCS ...
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... SIDE VIEW 0.08[0.003] C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.30[0.012] 0.50[0.020] 0°-12° C SEATING PLANE Figure 12-1. 56-Lead QFN LF56A CY7C64713/14 BOTTOM VIEW 0.18[0.007] 0.28[0.011] PIN1 ID N 0.20[0.008 0.45[0.018] E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0.24[0.009] (4X) ...
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... Package Diagrams (continued) Figure 12-2. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-08039 Rev. *B CY7C64713/14 51-85050-*A Page ...
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... The thickness of the solder paste template should be 5 mil recommended that “No Clean” type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. CY7C64713/14 51-85101-*B Page ...
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... PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 13-3. X-ray Image of the Assembly 2 C system, provided that the system conforms to the I CY7C64713/ Standard Specification Page ...
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... Document History Page Document Title: CY7C64713/4 EZ-USB FX1™ USB Microcontroller Full-Speed USB Peripheral Controller Document Number: 38-08039 Orig. of REV. ECN NO. Issue Date Change ** 132091 02/10/04 *A 230709 SEE ECN *B 307474 SEE ECN Document #: 38-08039 Rev. *B © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...