CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet - Page 19

• Manufacturer Part Number: CY7C64713
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 5-1. FX1 Pin Definitions (continued)
Document #: 38-08039 Rev. *B
TQFP
PORT D
Port E
128
102
103
104
105
121
122
123
124
108
109
110
77
78
79
TQFP
100
62
63
64
80
81
82
83
95
96
97
98
86
87
88
QFN
56
45
46
47
48
49
50
51
52
PD0 or
PD1 or
PD2 or
PD3 or
PD4 or
PD5 or
PD6 or
PD7 or
PE0 or
PE1 or
PC5 or
GPIFADR5
PC6 or
GPIFADR6
PC7 or
GPIFADR7
FD[8]
FD[9]
FD[10]
FD[11]
FD[12]
FD[13]
FD[14]
FD[15]
T0OUT
T1OUT
PE2 or
T2OUT
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default
[8]
(PC5)
(PC6)
(PC7)
(PD0)
(PD1)
(PD2)
(PD3)
(PD4)
(PD5)
(PD6)
(PD7)
(PE0)
(PE1)
(PE2)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT
outputs a high level for one CLKOUT clock cycle when Timer0 overflows.
If Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is
active when the low byte timer/counter overflows.
Multiplexed pin whose function is selected by the PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT
outputs a high level for one CLKOUT clock cycle when Timer1 overflows.
If Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is
active when the low byte timer/counter overflows.
Multiplexed pin whose function is selected by the PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT is active
(HIGH) for one clock cycle when Timer/Counter 2 overflows.
Description
CY7C64713/14
Page 19 of 50