CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet - Page 45

• Manufacturer Part Number: CY7C64713
• Manufacturer: CYPRESS [Cypress Semiconductor]

10.16.4 Sequence Diagram of a Single and Burst Asynchronous Write
Figure 10-21 diagrams the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single
write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND.
·At t = 0 the FIFO address is applied, insuring that it meets the setup time of t
may be tied low in some applications).
·At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of t
If the SLCS is used, it must be in asserted with SLWR or before SLWR is asserted.
·At t = 2, data must be present on the bus t
·At t = 3, deasserting SLWR will cause the data to be written from the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after t
The same sequence of events are shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note: In the
burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next
byte in the FIFO. The FIFO pointer is post incremented.
In Figure 10-21 once the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed
to the host using the PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same
time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The
FIFOADDR lines are to be held constant during the PKTEND assertion.
11.0
Table 11-1. Ordering Information
Document #: 38-08039 Rev. *B
Ideal for battery powered applications
CY7C64714-128AXC
CY7C64714-100AXC
CY7C64714-56LFXC
Ideal for non-battery powered applications
CY7C64713-128AXC
CY7C64713-100AXC
CY7C64713-56LFXC
CY3674
FIFOADR
PKTEND
FLAGS
SLWR
DATA
SLCS
Ordering Code
Ordering Information
t=0
t
SFA
t =1
t
Figure 10-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram
WRpwl
t=2
t
SFD
t=3
t
N
t
FDH
WRpwh
t
FAH
t
XFLG
128 TQFP – Lead-Free
100 TQFP – Lead-Free
56 QFN – Lead-Free
128 TQFP - Lead-Free
100 TQFP - Lead-Free
56 QFN - Lead-Free
EZ-USB FX1 Development Kit
XFLG
from the de-asserting edge of SLWR.
SFD
T=0
t
SFA
before the de-asserting edge of SLWR.
T=1
Package Type
t
WRpwl
T=2
t
SFD
T=3
t
N+1
FDH
t
WRpwh
T=4
t
WRpwl
T=5
t
SFD
T=6
t
N+2
FDH
t
WRpwh
WRpwl
SFA
. If SLCS is used, it must also be asserted (SLCS
T=7
RAM Size
and minimum de-active pulse width of t
t
WRpwl
16K
16K
16K
16K
16K
16K
T=8
t
SFD
T=9
t
t
N+3
WRpwh
FDH
# Prog I/Os
40
40
24
40
40
24
CY7C64713/14
t
PEpwl
[17]
t
XFLG
t
PEpwh
/Data Busses
t
FAH
Page 45 of 50
Address
16/8 bit
16/8 bit
8051
–
–
-
-
WRpwh
.