CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet - Page 32

• Manufacturer Part Number: CY7C64713
• Manufacturer: CYPRESS [Cypress Semiconductor]

10.3
Table 10-2. Data Memory Read Parameters
Document #: 38-08039 Rev. *B
t
t
t
t
t
t
t
t
Note:
16. t
CL
AV
STBL
STBH
SCSL
SOEL
DSU
DH
Parameter
t
t
t
t
ACC2
ACC2
ACC2
ACC3
ACC3
CLKOUT
Data Memory Read
(24 MHz) = 3*t
(48 MHz) = 3*t
(24 MHz) = 5*t
(48 MHz) = 5*t
CLKOUT
and t
ACC3
A[15..0]
A[15..0]
[14]
D[7..0]
D[7..0]
are computed from the above parameters as follows:
1/CLKOUT Frequency
Delay from Clock to Valid Address
Clock to RD LOW
Clock to RD HIGH
Clock to CS LOW
Clock to OE LOW
Data Setup to Clock
Data Hold Time
[14]
OE#
RD#
RD#
CS#
CS#
CL
CL
CL
CL
– t
– t
– t
– t
AV
AV
AV
AV
–t
– t
–t
– t
DSU
DSU
DSU
DSU
t
t
AV
AV
t
t
CL
CL
= 106 ns
= 190 ns
= 43 ns
= 86 ns.
Description
Figure 10-2. Data Memory Read Timing Diagram
t
STBL
t
t
ACC1
SCSL
t
SOEL
[16
Stretch = 0
Stretch = 1
t
data in
DSU
t
ACC1
Min.
[16]
9.6
t
0
STBH
t
DH
20.83
41.66
Typ.
83.2
t
AV
t
data in
DSU
Max.
10.7
11.1
13
11
11
t
DH
CY7C64713/14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 32 of 50
48 MHz
24 MHz
12 MHz
Notes