AD9915 AD [Analog Devices], AD9915 Datasheet - Page 21

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
CLOCK INPUT (REF_CLK/REF_CLK)
REF_CLK/ REF_CLK Overview
The
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK/ REF_CLK input pins. The REF_CLK input can be
driven directly from a differential or single-ended source. There
is also an internal phase-locked loop (PLL) multiplier that can
be independently enabled. However, the PLL limits the SYSCLK
signal between 2.4 GHz and 2.5 GHz operation. A differential
signal is recommended when the PLL is bypassed. A block
diagram of the REF_CLK functionality is shown in Figure 32.
Figure 32 also shows how the CFR3 control bits are associated
with specific functional blocks.
REF_CLK
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected,
the REF_CLK/ REF_CLK pins must be driven by an external
signal source (single-ended or differential). Input frequencies
up to 3.5 GHz are supported.
Direct Driven REF_CLK/ REF_CLK
With a differential signal source, the REF_CLK/ REF_CLK pins
are driven with complementary signals and ac-coupled with 0.1 µF
capacitors. With a single-ended signal source, either a single-
ended-to-differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either
case, 0.1 µF capacitors are used to ac couple both
REF_CLK/ REF_CLK pins to avoid disturbing the internal dc
bias voltage of ~1.35 V. See Figure 33 for more details.
The REF_CLK/ REF_CLK input resistance is ~2.5 kΩ differential
(~1.2 kΩ single-ended). Most signal sources have relatively low
output impedances. The REF_CLK/ REF_CLK input resistance
REF_CLK
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supports a number of options for producing the
CLOCK EDGE
DOUBLER
CFR3[16]
INPUT DIVIDER RATIO
CFR3[21:20]
÷ 1, 2, 4, 8
Figure 32. REF_CLK Block Diagram
DOUBLER ENABLE
2
×2
INPUT DIVIDER
RESET CFR3[22]
CFR3[19]
1
0
ENABLE
IN
CHARGE
CFR3[5:3]
PUMP
I
CP
LOOP_FILTER
PLL
2
FILTER
LOOP
DIVIDE
CFR3[15:8]
7
58
OUT
N
PLL ENABLE
CFR3[18]
1
0
SYSCLK
Rev. A | Page 21 of 48
is relatively high; therefore, its effect on the termination impedance
is negligible and can usually be chosen to be the same as the
output impedance of the signal source. The bottom two examples
in Figure 33 assume a signal source with a 50 Ω output impedance.
Phase-Locked Loop (PLL) Multiplier
An internal phase-locked loop (PLL) provides the option to use
a reference clock frequency that is significantly lower than the
system clock frequency. The PLL supports a wide range of
programmable frequency multiplication factors (8× to 255×) as
well as a programmable charge pump current and external loop
filter components (connected via the PLL LOOP_FILTER pin).
These features add an extra layer of flexibility to the PLL,
allowing optimization of phase noise performance and
flexibility in frequency plan development. The PLL is also
equipped with a PLL lock bit indicator (0x1B[24]).
The PLL output frequency range (f
range of 2.4 GHz ≤ f
VCO Calibration
When using the PLL to generate the system clock, VCO
calibration is required to tune the VCO appropriately and
achieve good performance. When the reference input signal is
stable, the VCO cal enable bit in the CFR1 register, 0x00[24],
must be asserted. Subsequent VCO calibrations require that the
VCO calibration bit be cleared prior to initiating another VCO
calibration. VCO calibration must occur before DAC
calibration to ensure optimal performance and functionality.
SINGLE-ENDED SOURCE,
SINGLE-ENDED SOURCE,
DIFFERENTIAL SOURCE,
SINGLE-ENDED INPUT
DIFFERENTIAL INPUT
DIFFERENTIAL INPUT
Figure 33. Direct Connection Diagram
SYSCLK
LVPECL,
DRIVER
≤ 2.5 GHz by the internal VCO.
PECL,
LVDS
OR
BALUN
50Ω
(1:1)
SYSCLK
TERMINATION
) is constrained to the
50Ω
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
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AD9915
REF_CLK
REF_CLK
REF_CLK
REF_CLK
REF_CLK
REF_CLK