AD9915 AD [Analog Devices], AD9915 Datasheet - Page 25

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
Normal Ramp Generation
Normal ramp generation implies that both no-dwell bits are
cleared (see the No-Dwell Ramp Generation section for details). In
Figure 38, a sample ramp waveform is depicted with the required
control signals. The top trace is the DRG output. The next trace
down is the status of the DROVER output pin (assuming that the
DRG over output enable bit is set). The remaining traces are
control bits and control pins. The pertinent ramp parameters
are also identified (upper and lower limits plus step size and Δt
for the positive and negative slopes). Along the bottom, circled
numbers identify specific events. These events are referred to by
number (Event 1 and so on) in the following paragraphs.
In this example, the positive and negative slopes of the ramp are
different to demonstrate the flexibility of the DRG. The
parameters of both slopes can be programmed to make the
positive and negative slopes the same.
Event 1—The digital ramp enable bit is set, which has no effect
on the DRG output because the bit is not effective until an I/O
update occurs.
Event 2—An I/O update registers the digital ramp enable bit. If
DRCTL = 1 is in effect (the gray portion of the DRCTL trace),
the DRG output immediately begins a positive slope (the gray
portion of the DRG output trace). Otherwise, if DRCTL = 0, the
DRG output is initialized to the lower limit.
Event 3—DRCTL transitions to Logic 1 to initiate a positive
slope at the DRG output. In this example, the DRCTL pin is
held long enough to cause the DRG to reach its programmed
upper limit. The DRG remains at the upper limit until the ramp
accumulator is cleared (DRCTL = 0) or the upper limit is
reprogrammed to a higher value. In the latter case, the DRG
immediately resumes its previous positive slope profile.
DIGITAL RAMP ENABLE
RAMP ACCUMULATOR
RAMP ACCUMULATOR
AUTOCLEAR DIGITAL
CLEAR DIGITAL
DRG OUTPUT
I/O_UPDATE
DRHOLD
DROVER
DRCTL
1
2
P DDS CLOCK CYCLES
3
+Δ
t
LOWER LIMIT
STEP SIZE
Figure 38. Normal Ramp Generation
POSITIVE
N DDS CLOCK CYCLES
Rev. A | Page 25 of 48
4
–Δ
t
Event 4—DRCTL transitions to Logic 0 to initiate a negative
slope at the DRG output. In this example, the DRCTL pin is
held long enough to cause the DRG to reach its programmed
lower limit. The DRG remains at the lower limit until DRCTL = 1,
or until the lower limit is reprogrammed to a lower value. In the
latter case, the DRG immediately resumes its previous negative
slope profile.
Event 5—DRCTL transitions to Logic 1 for the second time,
initiating a second positive slope.
Event 6—The positive slope profile is interrupted by DRHOLD
transitioning to Logic 1. This stalls the ramp accumulator and
freezes the DRG output at its last value.
Event 7—DRHOLD transitions to Logic 0, releasing the ramp
accumulator and reinstating the previous positive slope profile.
Event 8—The clear digital ramp accumulator bit is set, which
has no effect on the DRG because the bit is not effective until an
I/O update is issued.
Event 9—An I/O update registers that the clear digital ramp
accumulator bit is set, resetting the ramp accumulator and forcing
the DRG output to the programmed lower limit. The DRG output
remains at the lower limit until the clear condition is removed.
Event 10—The clear digital ramp accumulator bit is cleared,
which has no effect on the DRG output because the bit is not
effective until an I/O update is issued.
Event 11—An I/O update registers that the clear digital ramp
accumulator bit is cleared, releasing the ramp accumulator; and
the previous positive slope profile restarts.
Event 12—The autoclear digital ramp accumulator bit is set,
which has no effect on the DRG output because the bit is not
effective until an I/O update is issued.
STEP SIZE
NEGATIVE
5
6
UPPER LIMIT
7
8
9
1 DDS CLOCK CYCLE
10
11
12
13
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