AD9915 AD [Analog Devices], AD9915 Datasheet - Page 32

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. When the
in single bidirectional I/O mode, this pin does not output data
and is set to a high impedance state.
SYNCIO—Input/Output Reset
SYNCIO synchronizes the I/O port state machines without
affecting the contents of the addressable registers. An active
high input on the SYNCIO pin causes the current communication
cycle to abort. After SYNCIO returns low (Logic 0), another
communication cycle can begin, starting with the instruction
byte write.
I/O_UPDATE—Input/Output Update
The I/O update initiates the transfer of written data from
the serial or parallel I/O port buffer to active registers.
I/O_UPDATE is active on the rising edge, and its pulse width
must be greater than one SYNC_CLK period.
AD9915
SCLK
SDIO
SCLK
SCLK
SCLK
SDO
SDIO
SDIO
SDIO
CS
CS
CS
CS
I
I
7
7
I
7
I
7
I
I
6
6
I
6
I
6
I
INSTRUCTION CYCLE
INSTRUCTION CYCLE
I
5
INSTRUCTION CYCLE
INSTRUCTION CYCLE
5
I
5
I
5
Figure 45. 2-Wire Serial Port Read Timing, Clock Stall High
Figure 43. 3-Wire Serial Port Read Timing, Clock Stall Low
I
I
4
AD9915
4
I
4
Figure 44. Serial Port Write Timing, Clock Stall High
I
Figure 42. Serial Port Write Timing, Clock Stall Low
4
I
I
3
3
I
3
I
3
operates
I
I
2
2
I
2
I
2
I
Rev. A | Page 32 of 48
I
1
1
I
1
I
1
I
I
0
0
I
0
I
0
D
D
D
O7
7
SERIAL I/O TIMING DIAGRAMS
Figure 42 through Figure 45 provide basic examples of the timing
relationships between the various control signals of the serial
I/O port. Most of the bits in the register map are not transferred
to their internal destinations until assertion of an I/O update,
which is not included in the timing diagrams that follow.
Note that the SCLK stall condition between the instruction byte
cycle and data transfer cycle in Figure 42 to Figure 45 is not
required.
MSB/LSB TRANSFERS
The
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 0 in CFR1 (0x00). The default
format is MSB first. If LSB first is active, all data, including the
instruction byte, must follow LSB-first convention. Note that the
highest number found in the bit range column for each register is
the MSB, and the lowest number is the LSB for that register.
7
D
O7
D
D
6
AD9915
O6
D
D
DATA TRANSFER CYCLE
6
O6
DATA TRANSFER CYCLE
D
D
5
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
O5
D
D
5
O5
D
D
serial port can support both most significant bit
DON'T CARE
4
O4
D
D
4
O4
D
D
3
O3
D
D
3
O3
D
D
2
O2
D
D
2
O2
D
D
1
O1
D
D
1
O1
D
0
D
D
O0
D
O0
0
Data Sheet