PCA8534AH-Q900 NXP [NXP Semiconductors], PCA8534AH-Q900 Datasheet - Page 15

• Manufacturer Part Number: PCA8534AH-Q900
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA8534A_2
Product data sheet
7.10 Display RAM
If less than four backplane outputs are required the unused outputs can be left as an
open-circuit.
The display RAM is a static 60 × 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
Logic 1 in the RAM bit map indicates the on-state of the corresponding LCD segment,
logic 0 indicates the off-state.
The display RAM bit map,
backplane outputs BP0 to BP3, and the columns 0 to 59 which correspond with the
segment outputs S0 to S59. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,
and BP3 respectively.
When display data is transmitted to the PCA8534A the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples or
quadruples. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in
applies equally to other LCD types.
Fig 9.
•
•
•
•
•
•
In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
the bits in the RAM bitmap and the LCD elements
the RAM columns and the segment outputs
the RAM rows and the backplane outputs.
backplane outputs
display RAM bits
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Display RAM bit map
(rows)/
(BP)
All information provided in this document is subject to legal disclaimers.
0
1
2
3
Rev. 02 — 1 June 2010
0
Figure
1
2
display RAM addresses (columns)/segment outputs (S)
9, shows the rows 0 to 3 which correspond with the
Figure
3
4
Universal LCD driver for low multiplex rates
10; the RAM filling organization depicted
55
PCA8534A
56
© NXP B.V. 2010. All rights reserved.
57
001aah617
58
59
15 of 44