DP8570 NSC [National Semiconductor], DP8570 Datasheet - Page 12

• Manufacturer Part Number: DP8570
• Description: Timer Clock Peripheral (TCP)
• Manufacturer: NSC [National Semiconductor]

Functional Description
the chip is unlocked but only after another 30 s min
63
sure that his system is stable when power has returned
The power fail circuitry contains active linear circuitry that
draws supply current from V
undesirable so this circuit can be disabled by masking the
power fail interrupt The power fail input can perform all
lock-out functions previously mentioned except that no ex-
ternal interrupt will be issued Note that the linear power fail
circuitry is switched off automatically when using V
standby mode
LOW BATTERY INITIAL POWER ON DETECT AND
POWER FAIL TIME SAVE
There are three other functions provided on the DP8570A to
ease power supply control These are an initial Power On
detect circuit which also can be used as a time keeping
failure detect a low battery detect circuit and a time save
on power failure
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero This
indicates that an oscillator fail event has occurred and time
keeping has failed
The Oscillator Fail flag will not be reset until the real-time
clock is started This allows the system to discriminate be-
tween an initial power-up and recovery from a power failure
If the battery backed mode is selected then bit D6 of the
Periodic Flag Register must be written low This will not af-
fect the contents of the Oscillator Fail Flag
Another status bit is the low battery detect This bit is set
only when the clock is operating under the V
when the battery voltage is determined to be less than 2 1V
(typical) When the power fail interrupt enable bit is low it
disables the power fail circuit and will also shut off the low
battery voltage detection circuit as well
To relieve CPU overhead for saving time upon power failure
the Time Save Enable bit is provided to do this automatical-
ly (See also Reading the Clock Latched Read ) The Time
Save Enable bit when set causes the Time Save RAM to
follow the contents of the clock This bit can be reset by
software but if set before a power failure occurs it will auto-
matically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin) Thus writing a one to the Time Save bit enables both a
software write or power fail write
SINGLE POWER SUPPLY APPLICATIONS
The DP8570A can be used in a single power supply applica-
tion To achieve this the V
ground and the power connected to V
The Oscillator Failed Single Supply bit in the Periodic Flag
Register should be set to a logic 1 which will disable the
oscillator battery reference circuit The power fail interrupt
should also be disabled This will turn off the linear power
fail detection circuits and will eliminate any quiescent power
drawn through these circuits Until the crystal select bits are
initialized the DP8570A may consume about 50 A due to
arbitrary oscillator selection at power on
(This extra 50
mode is selected)
s max debounce time The system designer must en-
A is not consumed if the battery backed
CC
BB
In some cases this may be
pin must be connected to
(Continued)
CC
and PFAIL pins
CC
pin and
BB
in
12
Figure 7 shows the functional block diagram of one of the
TIMER FUNCTIONAL DESCRIPTION
The DP8570A contains 2 independent multi-mode timers
Each timer is composed of a 16-bit negative edge triggered
binary down counter and associated control The operation
is similar to existing P peripheral timers except that several
features have been enhanced The timers can operate in
four modes and in addition the input clock frequency can
be selected from a prescaler over a wide range of frequen-
cies Furthermore these timers are capable of generating
interrupts as well as hardware output signals and both the
interrupt and timer outputs are fully programmable active
high or low open drain or push-pull
timers The timer consists of a 16-bit counter two 8-bit input
registers two 8-bit output registers clock prescaler mode
control logic and output control logic The timer and the
data registers are organized as two bytes for each timer
Under normal operations a read write to the timer locations
will read or write to the data input register The timer con-
tents can be read by setting the counter Read bit (RD) in the
timer control register
TIMER INITIALIZATION
The timer’s operation is controlled by a set of registers as
listed in Table III These consist of 2 data input registers and
one control register per timer The data input registers con-
tain the timers count down value The Timer Control Regis-
ter is used to set up the mode of operation and the input
clock rate The timer related interrupts can be controlled by
programming the Interrupt Routing Register and Interrupt
Control Register 0 The timer outputs are configured by the
Output Mode Register
All these registers must be initialized prior to starting the
timer(s) The Timer Control Register should first be set to
select the timer mode with the timer start stop bit reset
Then when the timer is to be started the control register
should be rewritten identically but with the start stop bit set
TIMER OPERATION
Each timer is capable of operation in one of four modes As
mentioned these modes are programmed in each timer’s
Control Register which is described later All four modes
operate in a similar manner They operate on the two 8-bit
data words stored into the Data Input Register At the begin-
ning of a counting cycle the 2 bytes are loaded into the timer
and the timer commences counting down towards zero The
exact action taken when zero is reached depends on the
mode selected but in general the timer output will change
state and an interrupt will be generated if the timer inter-
rupts are unmasked
Timer 0 Data MSB
Timer 0 Data LSB
Timer 0 Control Register
Timer 1 Data MSB
Timer 1 Data LSB
Timer 1 Control Register
Interrupt Routing Register
Interrupt Control Reg 0
Output Mode Register
Register Name
TABLE III Timer Associated Registers
Register
Select
X
X
0
X
X
0
0
1
1
Select
Page
0
0
0
0
0
0
0
0
0
Address
0FH
10H
01H
12H
11H
02H
04H
03H
02H