DP8570 NSC [National Semiconductor], DP8570 Datasheet - Page 15

• Manufacturer Part Number: DP8570
• Description: Timer Clock Peripheral (TCP)
• Manufacturer: NSC [National Semiconductor]

Functional Description
MODE 3 RETRIGGERABLE ONE SHOT
This mode is different from the previous three modes in that
this is the only mode which uses the external gate to trigger
the output Once the timer Start Stop bit is set the output
stays inactive and nothing happens until a positive tran-
sition is received on the G1 or G0 pins or the Count Hold
Gate (CHG) bit is set in the timer control register When a
transition ocurs the one shot output is set active immediate-
ly the counter is loaded with the value in the input register
on the next transition of the input clock and the countdown
begins If a retrigger occurs regardless of the current coun-
ter value the counters will be reloaded with the value in the
input register and the counter will be restarted without
changing the output state See Figure 11 A trigger count
can occur at any time during the count cycle and can be a
hardware or software signal (G0 G1 or CHG) In this mode
the timer will output a single pulse whose width is deter-
mined by the value in the input data register (N) and the
input clock period
Pulse Width
Before entering mode 3 if a spurious edge has occurred on
G0 G1 or the CHG bit is set to logic 1 then a pulse will
appear at MFO or T1 or INTR output pin when the timer is
started To ensure this does not happen do the following
steps before entering mode 3 Configure the timer for mode
0 load a count of zero then start the timer
The timer will generate an interrupt only when it reaches a
count of zero This timer mode is useful for continuous
‘‘watch dog’’ timing line frequency power failure detection
etc
READING THE TIMERS
National has discovered that some users may encounter
unacceptable error rates for their applications when reading
the timers on the fly asynchronously When doing asynchro-
nous reads of the timers an error may occur The error is
that a successive read may be larger than the previous
FIGURE 10 Timing Waveforms for Timer Mode 2
(Timer Output Programmed Active High)
e
Clock Period
FIGURE 11 Timing Waveforms for Timer Mode 3 Output Programmed Active High
c
N
(Continued)
TL F 8638 – 12
15
read Experimental results indicate that the typical error rate
Is approximately one per 29 000 under the following condi-
tions
Timer clock frequency of 5 MHz
Computer 386 33 MHz PC AT
Program
Those users who find the error rate unacceptable may re-
duce the problem effectively to zero by employing a hard-
ware work-around that synchronizes the writing of the read
bit to the timer control register with respect to the decre-
menting clock Refer to Figure 1 in Appendix A for a sug-
gested hardware work-around
A software work-around can reduce the errors but not as
substantial as a hardware work-around Software work-
arounds are based on observations that the read following a
bad read appeared to be valid
This problem concerns statistical probability and is similar to
metastability issues For more information on metastability
refer to 1991 IEEE transactions on Custom Integrated Cir-
cuits Conference paper by T J Gabara of AT T Bell Labo-
ratories page 29 4 1
Normally reading the timer data register addresses 0FH
and 10H for Timer 0 and 11H and 12H for Timer 1 will result
in reading the input data register which contains the preset
value for the timers
To read the contents of a timer the P first sets the timer
read bit in the appropriate Timer Control Register high This
will cause the counters contents to be latched to 2-bit– 8-bit
output registers and will enable these registers to be read if
the
reading the LSB byte the timer read bit is internally reset
and subsequent reads of the timer locations will return the
input register values
DETAILED REGISTER DESCRIPTION
There are 5 external address bits Thus the host microproc-
essor has access to 32 locations at one time An internal
switching scheme provides a total of 67 locations
This complete address space is organized into two pages
Page 0 contains two blocks of control registers timers real
time clock counters and special purpose RAM while page
1 contains general purpose RAM Using two blocks enables
the 9 control registers to be mapped into 5 locations The
only register that does not get switched is the Main Status
Register It contains the page select bit and the register
select bit as well as status information
A memory map is shown in Figure 2 and register addressing
in Table VII They show the name address and page loca-
tions for the DP8570A
P reads the timers input data register addresses On
Microsoft ‘‘C’’ 6 0 reading and saving timer con-
tents in a continuous loop
TL F 8638 – 13