DP8570 NSC [National Semiconductor], DP8570 Datasheet - Page 19

• Manufacturer Part Number: DP8570
• Description: Timer Clock Peripheral (TCP)
• Manufacturer: NSC [National Semiconductor]

Functional Description
D0 This bit when set to a one makes the T1 (timer 1)
output pin active high and when set to a zero it makes this
pin active low
D1 This bit controls whether the T1 pin is an open drain or
push-pull output A one indicates push pull
D2 This bit when set to a one makes the INTR output pin
active high and when set to a zero it makes this pin active
low
D3 This bit controls whether the INTR pin is an open drain
or push-pull output A one indicates push-pull
D4 This bit when set to a one makes the MFO output pin
active high and when set to a zero it makes this pin active
low
D5 This bit controls whether the MFO pin is an open drain
or push-pull output A one indicates push-pull
D6 and D7 These bits are used to program the signal ap-
pearing at the MFO output as follows
INTERRUPT CONTROL REGISTER 0
If battery backed mode is selected and the DP8570A is in
standby (V
the Real Time Mode Register
D0–D5 These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit
These interrupts are issued at the rollover of the clock For
example the minutes interrupt will be issued whenever the
minutes counter increments In all likelihood the interrupt
will be enabled asynchronously with the real time change
Therefore the very first interrupt will occur in less than the
BB l
D7 D6
0
0
1
V
X
0
1
CC
) then all bits are controlled by D4 of
2nd Interrupt
Timer 0 Waveform
Buffered Crystal Oscillator
MFO Output Signal
(Continued)
TL F 8638 – 20
19
periodic time chosen but after the first interrupt all subse-
quent interrupts will be spaced correctly These interrupts
are useful when minute second real time reading or task
switching is required When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin
D6 and D7 These are individual timer enable bits A one
written to these bits enable the timers to generate interrupts
to the P
INTERRUPT CONTROL REGISTER 1
D0– D5 Each of these bits are enable bits which will enable
a comparison between an individual clock counter and its
associated compare RAM If any bit is a zero then that
clock-RAM comparator is set to the ‘‘always equal’’ state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM However to ensure that an alarm
interrupt is not generated at bit D3 of the Main Status Regis-
ter all bits must be written to a logic zero
D6 In order to generate an external alarm compare inter-
rupt to the P from bit D3 of the Main Status Register this
bit must be written to a logic 1 If battery backed mode is
selected and the DP8570A is in standby (V
this bit is controlled by D4 of the Real Time Mode Register
D7 The MSB of this register is the enable bit for the Power
Fail Interrupt When this bit is set to a one an interrupt will
be generated to the P when PFAIL
mode is selected and the DP8570A is in standby
(V
Time Mode Register
This bit also enables the low battery detection analog cir-
cuitry
If the user wishes to mask the power fail interrupt but utilize
the analog circuitry this bit should be enabled and the
Routing Register can be used to route the interrupt to the
MFO pin The MFO pin can then be left open or configured
as the Timer 0 or buffered oscillator output
BB l
V
CC
) then this bit is controlled by D4 of the Real
e
0 If battery backed
BB l
TL F 8638 – 21
V
CC
) then