AD9253-125EBZ AD [Analog Devices], AD9253-125EBZ Datasheet - Page 25

• Manufacturer Part Number: AD9253-125EBZ
• Description: Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
• Manufacturer: AD [Analog Devices]

Data Sheet
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 67).
Input Clock Divider
The
to divide the input clock by integer values between 1 and 8.
The
external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a vari-
ety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9253. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 64.
AD9253
AD9253
AD9253
contains an input clock divider with the ability
clock divider can be synchronized using the
contains a duty cycle stabilizer (DCS) that retimes
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
50kΩ
50kΩ
Figure 67. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Figure 65. Differential PECL Sample Clock (Up to 1 GHz)
Figure 66. Differential LVDS Sample Clock (Up to 1 GHz)
50Ω
1
50Ω RESISTOR IS OPTIONAL.
0.1µF
1
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ
50kΩ
V
CC
1kΩ
1kΩ
PECL DRIVER
LVDS DRIVER
CMOS DRIVER
AD951x
AD951x
Rev. 0 | Page 25 of 40
AD951x
240Ω
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
OPTIONAL
240Ω
100Ω
0.1µF
100Ω
100Ω
80
75
70
65
60
55
0.1µF
0.1µF
0.1µF
0.1µF
40
0.1µF
42
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC
44
Figure 64. SNR vs. DCS On/Off
46
DUTY CYCLE (%)
48
SNRFS (DCS OFF)
50
SNRFS (DCS ON)
52
54
56
58
AD9253
60