AD9253-125EBZ AD [Analog Devices], AD9253-125EBZ Datasheet - Page 26

• Manufacturer Part Number: AD9253-125EBZ
• Description: Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
• Manufacturer: AD [Analog Devices]

Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 68).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9253.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the
Application Note
performance as it relates to ADCs.
AD9253
A
) due only to aperture jitter (t
SNR Degradation = 20 log
130
120
100
110
90
80
70
60
50
40
30
1
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 68. Ideal SNR vs. Input Frequency and Jitter
AN-501 Application Note
for more in-depth information about jitter
ANALOG INPUT FREQUENCY (MHz)
10
0.125ps
10
0.25ps
J
0.5ps
1.0ps
2.0ps
) can be calculated by




2


and the
1
f
100
A

t
J




AN-756
14 BITS
12 BITS
16 BITS
1000
Rev. 0 | Page 26 of 40
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 69, the power dissipated by the
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
The
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 2 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times. When
using the SPI port interface, the user can place the ADC in
power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details on using these features.
AD9253
350
300
250
200
150
100
Figure 69. Analog Core Power vs. f
10
20
is placed in power-down mode either by the SPI
20 MSPS
30
40
40 MSPS
50
SAMPLE RATE (MSPS)
50 MSPS
AD9253
60
70
65 MSPS
80
to its normal operating
SAMPLE
80 MSPS
90
for f
100 110 120
105 MSPS
IN
= 10.3 MHz
Data Sheet
125 MSPS
AD9253
130
is