AD9253-125EBZ AD [Analog Devices], AD9253-125EBZ Datasheet - Page 5

• Manufacturer Part Number: AD9253-125EBZ
• Description: Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
• Manufacturer: AD [Analog Devices]

Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (PDWN, SYNC, SCLK)
LOGIC INPUT (CSB)
LOGIC INPUT (SDIO)
LOGIC OUTPUT (SDIO)
DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644
DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER,
1
2
3
See the
This is specified for LVDS and LVPECL only.
This is specified for 13 SDIO/OLM pins sharing the same connection.
Logic Compliance
Differential Input Voltage
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
REDUCED SIGNAL OPTION
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
AN-835 Application
1
OH
OL
= 50 μA)
= 800 μA)
3
Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
OS
OS
2
)
)
OD
OD
)
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Rev. 0 | Page 5 of 40
Min
0.2
AGND − 0.2
1.2
0
1.2
0
1.2
0
290
1.15
160
1.15
CMOS/LVDS/LVPECL
Twos complement
Twos complement
Typ
0.9
15
4
30
2
26
2
26
5
1.79
LVDS
345
1.25
LVDS
200
1.25
Max
3.6
AVDD + 0.2
AVDD + 0.2
0.8
AVDD + 0.2
0.8
AVDD + 0.2
0.8
0.05
400
1.35
230
1.35
AD9253
Unit
V p-p
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V