MAX5893EGK MAXIM [Maxim Integrated Products], MAX5893EGK Datasheet - Page 15

• Manufacturer Part Number: MAX5893EGK
• Description: 12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
• Manufacturer: MAXIM [Maxim Integrated Products]

Programming its registers with the SPI serial interface
sets the MAX5893 operation modes. Table 2 shows all
Table 2. MAX5893 Programmable Registers
Conditions in bold are default states after reset.
ADD
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
12-Bit, 500Msps Interpolating and Modulating
Unused
Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation
01 = 2x interpolation
10 = 4x interpolation
11 = 8x interpolation
0 = Two’s
complement
input data
1 = Offset
binary input
data
Unused
8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
Unused
10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB
bits in 07h register. Default: 000h
IDAC IOFFSET
Direction
0 = Current on
OUTIN
1 = Current on
OUTIP
8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
Unused
10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the
LSB bits in 0Bh register. Default: 000h
QDAC
IOFFSET
Direction
0 = Current on
OUTQN
1 = Current on
OUTQP
Reserved, do not write to these bits.
Reserved, do not write to these bits.
Reserved, do not write to these bits.
BIT 7
______________________________________________________________________________________
0 = Single
port (A),
interleaved
I/Q
1 = Dual port
I/Q input
0 = MSB first
1 = LSB first
Unused
Unused
BIT 6
Programming Registers
Software Reset
0 = Normal
1 = Reset all
registers
Third
Interpolation
Filter
Configuration
0 = Lowpass
1 = Highpass
0 = Clock output
on DATACLK
1 = Clock output
on D ATAC LK/B10
BIT 5
Interpolator
Power-Down
0 = Normal
1 = Power-down
Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = f
10 = f
11 = f
0 = Input data
latched on
rising clock
edge
1 = Input data
latched on falling
clock edge
Dual DAC with CMOS Inputs
BIT 4
IM
IM
IM
/ 2
/ 4
/ 4
of the registers. The following are descriptions of each
register.
IDAC Power-
Down
0 = Normal
1 = Power-down
0 = Data clock
input enabled
1 = Data clock
output enabled
4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
BIT 3
QDAC Power-
Down
0 = Normal
1 = Power-down
Mixer Modulation
Mode
0 = Complex
1 = Real
Data
Synchronizer
0 = Enabled
1 = Disabled
BIT 2
Unused
Modulation
Sign
0 = e
1 = e
Unused
IDAC Offset
Adjustment
Bit 1
(see 06h
register)
QDAC Offset
Adjustment
Bit 1
(see 0Ah
register)
BIT 1
-jω
+jω
Unused
IDAC Offset
Adjustment
Bit 0
(see 06h
register)
QDAC Offset
Adjustment
Bit 0
(see 0Ah
register)
BIT 0
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