MAX5893EGK MAXIM [Maxim Integrated Products], MAX5893EGK Datasheet - Page 17

• Manufacturer Part Number: MAX5893EGK
• Description: 12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
• Manufacturer: MAXIM [Maxim Integrated Products]

Address 07h
Bit 7
Address 08h
Bits 7–0 These 8 bits define the binary number for
Address 09h
Bits 3–0 These four bits define the binary number for
Address 0Ah, Bits 7 to 0; Address 0Bh, Bit 1 and Bit 0
Address 0Bh
Bit 7
Offset adjustment is achieved by adding a digital code
to the DAC inputs. The code OFFSET (see equation
below), as stored in the relevant control registers, has a
range from 0 to 1023 and a sign bit. The applied DAC
offset is 4 times the code stored in the register, provid-
ing an offset adjustment range of ±255 LSB codes. The
resolution is 1 LSB.
Gain trimming is done by varying the full-scale current
according to the following formula:
where I
Reference section). COARSE is the register content of
registers 05h and 09h for the I- and Q-channel, respec-
tively. FINE is the register content of register 04h and
08h for the I- and Q-channel, respectively. The range of
coarse is from 0 to 11, with 11 being the default. The
I
OUTFS
12-Bit, 500Msps Interpolating and Modulating
REF
=
Logic 0 (default) adds the 10 bits offset to
OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.
⎡
⎢
⎣
Logic 0 (default) adds the 10 bits offset cur-
rent to OUTIN. A logic 1 adds the 10 bits off-
set current to OUTIP.
fine-gain adjustment of the QDAC full-scale
current (see the Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
the coarse-gain adjustment of the QDAC full-
scale current (see the Gain Adjustment sec-
tion). Bit 3 is the MSB. Default is all ones.
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the Offset Adjustment
section). Default is all zeros.
⎛
⎜
⎝
I
OFFSET
3
is the reference current (see the Internal
×
I
4
REF
⎞
⎟
⎠
______________________________________________________________________________________
⎛
⎜
⎝
COARSE
=
4
16
×
OFFSET
2
+
16
1
⎞
⎟
⎠
−
⎛
⎜
⎝
3
×
×
32
Offset Adjustment
I
REF
I
OUTFS
⎞
⎟
⎠
⎛
⎜
⎝
FINE
256
Gain Trim
⎞
⎟
⎠
⎤
⎥
⎦
⎛
⎜
⎝
Dual DAC with CMOS Inputs
1024
24
⎞
⎟
⎠
range for FINE is from 0 to 255 with 0 being the default.
Given this, the gain can be adjusted in steps of approx-
imately 0.01dB.
The MAX5893 is capable of capturing data in single-
port and dual-port modes (selected through bit 6,
address 02h). In single-port mode, the data for both
channels is input through the A port (A11–A0).
The channel for the input data is determined through
the state of the SELIQ/B11 (pin 26) bit. When SELIQ is
set to logic-high, the input data is presented to the
I-channel, when set to logic-low, the input data is
presented to the Q-channel. The unused B-port inputs
(DATACLK/B10, B9–B0) should be grounded when run-
ning in single-port mode.
Dual-port mode, as the name implies, requires that
each channel receives its data from a separate data
bus. SELIQ/B11 and DATACLK/B10 revert to data bit
inputs for the Q-channel in dual-port mode.
The MAX5893 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data in either single-port or dual-port
mode. Table 3 shows the corresponding DAC output
levels when using signed or unsigned data modes.
Data synchronization circuitry is provided to allow oper-
ation with an input data clock. The data clock must be
frequency locked to the DAC clock (f
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to ±1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least 4 clock cycles.
Subsequently, the MAX5893 monitors the phase rela-
Table 3. DAC Output Code Table
0000 0000 0000
0111 1111 1111
1111 1111 1111
(UNSIGNED)
Single-Port/Dual-Port Data Input Modes
OFFSET
BINARY
DIGITAL INPUT CODE
Data Synchronization Modes
COMPLEMENT
1000 0000 0000
0000 0000 0000
0111 1111 1111
(SIGNED)
TWO'S
I
OUT_P
OUTFS
I
OUTFS
0
2
DAC
/
), but can
I
OUT_N
I
OUTFS
OUTFS
2
0
17
/