MAX5893EGK MAXIM [Maxim Integrated Products], MAX5893EGK Datasheet - Page 18

• Manufacturer Part Number: MAX5893EGK
• Description: 12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
• Manufacturer: MAXIM [Maxim Integrated Products]

tionship and detects if the phase drifts more than ±1
data clock cycle. If this occurs, the synchronizer auto-
matically reestablishes synchronization. However, dur-
ing the resynchronization phase, up to 8 data words
may be lost or repeated.
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.
The MAX5893 has a main DATACLK available at
pin 14. An alternate DATACLK is available at pin 27
(DATACLK/B10) when configured in single-port data
input mode (bit 5, address 02h). The DATACLK can be
configured to accept an input clock signal for latching
the input data, or to source a clock signal that can drive
up to 10pF load while latching the input data (bit 3,
address 02h). If DATACLK is configured as an output, it
is frequency divided from the CLKP/CLKN input,
depending on the operating mode, see Table 4.
12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Figure 4. Data Input Timing Diagram
18
______________________________________________________________________________________
A0–A11/B0–B11
CLKP–CLKN
DATACLK
DATACLK Modes
t
D
t
CLK
The MAX5893 can be configured to latch the input
data on either the rising edge or falling edge of the
DATACLK signal (bit 4, address 02h). Figure 4 shows
the timing requirements between the DATACLK signal
and the input data bus with latching on the rising edge.
Table 4. Clock Frequency Ratios in
Various Modes
Dual Port
INPUT
MODE
Single
Port
t
DS
INTERPOLATION
RATE
1x
2x
4x
8x
1x
2x
4x
8x
t
DH
f
DATA
1:1
1:1
1:2
1:4
1:1
1:2
1:4
1:8
:f
CLK
f
DAC
1:2
1:1
1:1
1:1
1:1
1:1
1:1
1:1
:f
CLK