CS5112YDWF24 ONSEMI [ON Semiconductor], CS5112YDWF24 Datasheet - Page 6

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CS5112YDWF24

Manufacturer Part Number
CS5112YDWF24
Description
1.4 A Switching Regulator with 5.0 V, 100 mA Linear Regulator with Watchdog, RESET and ENABLE
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

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CS5112YDWF24
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bandgap voltage reference, and a composite pass transistor.
When an unregulated voltage greater than 6.6 V is applied
to the V
present at V
regulator, the I
resistor to ground. A 100 mF or larger capacitor with an ESR
< 8.0 W must be connected between V
operate the 5.0 V linear regulator as an independent
regulator (i.e. separate from the switching supply), the input
voltage must be tied to the V
on. Q
base current for Q
V
capacitor, C
amplifier becomes biased and provides the appropriate
amount of base current to Q
the scaled output voltage via an internal voltage divider, R
through R
reference. The error amplifier output or error signal is an
output current equal to the error amplifier’s input
differential voltage times the transconductance of the
amplifier. Therefore, the error amplifier varies the base
current to Q
difference between the reference voltage and the scaled
V
(WDI) from the microprocessor. It responds to the falling
LIN
LIN
The 5.0 V linear regulator consists of an error amplifier,
The 5.0 V linear regulator circuitry is shown in Figure 6.
As the voltage at the V
The watchdog timer circuitry monitors an input signal
, begins to rise as Q
1
output voltage.
provides base drive for Q
V
I
R
64.9 kW
REG
BIAS
REG
BIAS
C
5
Delay
1
OUT
, and compares it to the bandgap voltage
LIN
, which provides bias to Q
input, a 5.0 V regulated DC voltage will be
5.0 V LINEAR REGULATOR
BIAS
. Once V
. For proper operation of the 5.0 V linear
CONTROL FUNCTIONS
WDI
3
. As Q
lead must have a 64.9 kW pull down
Figure 6. Block Diagram of 5.0 V Linear Regulator Portion of the CS5112
3
REG
LIN
’s output current charges the output
3
is turned on, the output voltage,
Reference
Bandgap
1
rises to a certain level, the error
. The error amplifier monitors
REG
input is increased, Q
lead.
2
which in turn provides
2
and Q
LIN
1.25 V
and ground. To
3
, based on the
CIRCUIT DESCRIPTION
1
Watchdog Timer
is turned
+
http://onsemi.com
RESET &
Linear
Error
Amplifier
Temperature
CS5112
2
Current
Limit
Over
6
edge of this watchdog signal which it expects to see within
an externally programmable time (see Figure 7).
ranging from 6.25 ms to 11 ms assuming ideal components.
Based on this, the software must be written so that the
watchdog arrives at least every 6.25 ms. In practice, the
tolerance of C
when calculating the minimum watchdog time (t
specified time a reset pulse train is issued until the correct
watchdog signal is received. The nominal reset signal in this
case is a 5 volt square wave with a 50% duty cycle as shown
in Figure 8.
RESET
R
1
The watchdog time is given by:
Using C
If a correct watchdog signal is not received within the
V
WDI
V
REG
LIN
Q
1
Figure 7. Timing Diagram for Normal
Delay
Q
2
t WDI + 1.353
t
Delay
POR
= 0.1 mF and R
Regulator Operation
and R
Q
R
R
R
R
3
2
3
4
5
BIAS
Normal Operation
BIAS
C Delay R BIAS
must be taken into account
V
LIN
= 64.9 kW gives a time
C
ESR < 8.0 W
OUT
RESET
= 100 mF
WDI
).

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