CS5112YDWF24 ONSEMI [ON Semiconductor], CS5112YDWF24 Datasheet - Page 9

• Manufacturer Part Number: CS5112YDWF24
• Description: 1.4 A Switching Regulator with 5.0 V, 100 mA Linear Regulator with Watchdog, RESET and ENABLE
• Manufacturer: ONSEMI [ON Semiconductor]

switching power supply operating in the discontinuous mode.
Step 1
Step 2
an external resistor value, R
Step 3
divider as follows (Figure 13).
R
and then calculate R
Step 4
oscillator frequency and V
all of the stored energy in the inductor is transferred to the
load prior to the next cycle. Since the current through the
inductor cannot change instantaneously and the inductance
is constant, a volt−second balance exists between the on time
and off time. The voltage across the inductor during the on
cycle is V
off cycle is V
EQ
This section outlines a procedure for designing a boost
Determine the output power required by the load.
Choose C
Next select the output voltage feedback sense resistor
For V
For V
Then find R
Determine the maximum on time at the minimum
DESIGN PROCEDURE FOR BOOST TOPOLOGY
where:
Figure 13. Feedback Sense Resistor Divider
FB1
FB2
Connected Between V
IN
R
OSC
active, choose a value for R
active, find:
EQ
and the voltage across the inductor during the
OUT
3
V FB1 + V OUT
R 2 +
, where:
based on the target oscillator frequency with
− V
P OUT + I OUT V OUT
2
R 3 + R EQ * R 2
R EQ +
V
V R2
I R2
IN
where:
R2
.
V
+
IN
OUT
BIAS
. For discontinuous operation,
V OUT
V FB1 * V FB2
V FB1
R
R
R
V FB1 R EQ
1
2
3
R 1 ) R EQ
R 1
OUT
= 64.9 kW. (See Figure 5).
* 1
R EQ
and Ground
1
V
V
and then solve for
FB1
FB2
APPLICATION NOTES
http://onsemi.com
(1)
(2)
(3)
(4)
(5)
CS5112
9
where the maximum on time is:
Step 5
discontinuous operation:
where η = efficiency.
dissipation should be calculated after the peak current has
been determined in Step 6. If the efficiency is less than
originally assumed, decrease the efficiency and recalculate
the maximum inductance and peak current.
Step 6
inductance, minimum V
sure the inductor current doesn’t exceed 1.4 A.
Step 7
ESR based on the allowable output voltage ripple.
capacitance value to obtain a low ESR. By placing
capacitors in parallel, the equivalent ESR can be reduced.
Step 8
under all operating conditions. To do this, we calculate the
modulator gain and the feedback resistor network
attenuation and set the gain of the error amplifier so that the
overall loop gain is 0 dB at the crossover frequency, f
addition, the gain slope should be −20 dB/decade at the
crossover frequency.
amplifier output to output voltage) is:
where:
I PK(MAX) +
Therefore:
Calculate the maximum inductance allowed for
Usually η = 0.75 is a good starting point. The IC’s power
Determine the peak inductor current at the minimum
Determine the minimum output capacitance and maximum
In practice, it is normally necessary to use a larger
Compensate the feedback loop to guarantee stability
The low frequency gain of the modulator (i.e. error
t ON(MAX) [ 1 *
L (MAX) +
DV OUT
DV EA
V IN t ON + (V OUT * V IN )t OFF
C OUT(MIN) +
V EA(MAX) G CSA
I PK +
ESR (MIN) +
f SW(MIN) V IN 2 (MIN) t ON 2 (MAX)
+
R S
V IN(MIN) t ON(MAX)
V EA(MAX)
I PK(MAX)
IN
V OUT(MAX)
and maximum on time to make
V IN(MIN)
L (MIN)
2P OUT h
8fDV RIPPLE
DV RIPPLE
I PK
+
I PK
R LOAD Lf
150 mW
2.4 V 7
f SW(MIN)
2
1
+ 2.3 A
CO
(10)
(12)
(13)
(11)
. In
(6)
(7)
(8)
(9)