LM12434CIWM NSC [National Semiconductor], LM12434CIWM Datasheet - Page 32

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LM12434CIWM

Manufacturer Part Number
LM12434CIWM
Description
Sign Data Acquisition System with Serial I/O and Self-Calibration
Manufacturer
NSC [National Semiconductor]
Datasheet
D15
D15
D15
6 0 Operational Information
INSTRUCTION RAM (Read Write) (Continued)
Limits
D7 –D0
D8
D9
D15 –D10 Don’t Care
INTERRUPT ENABLE REGISTER (Read Write)
Bits
D0
D1
D2
D3
D4
D5
D6
D7
D10 –D8
D15 –D11 Programmable number of conversion results in the FIFO to generate an interrupt
TIMER REGISTER (Read Write)
The Timer delays the execution of an instruction if the Timer bit is set in that instruction
The time delay is
Delay
e
0 to 7 enable interrupt generation for the following conditions when the bit is set to 1
D14
D14
Generate Interrupt (INT2)
D14
1
Number of Conversion
(32
Results in FIFO to
Limit 8-bit limit value
Sign Sign of limit value 0
interrupt
INT0 Generates an interrupt when a limit is passed in watchdog mode
INT1 Generates an interrupt when the sequencer has loaded the instruction number contained in bits D10 D9 and
D8 of the Interrupt Enable register
INT2 Generates an interrupt when the number of conversion results in the FIFO is equal to the programmed value
(D15 –D11)
INT3 Generates an interrupt when an auto-zero cycle is completed
INT4 Generates an interrupt when a full calibration cycle is completed
INT5 Generates an interrupt when a pause condition is encountered
This bit is a don’t care condition No interrupt is associated with this bit
INT7 Generates an interrupt when the chip is returned from standby and is ready for operation
Programmable instruction number used to generate an interrupt when that instruction has been reached
l k
2
c
D13
D13
D13
N)
FIGURE 9 Bit Assignments for LM12434 and LM12 L 438 Internal Registers (Continued)
Don’t Care
High Limit Low limit 0
a
2 Clock Cycles
D12
D12
D12
D11
D11
D11
e
D10
Positive 1
D10
D10
e
Instruction Number
Inputs lower than limit generate interrupt 1
Interrupt (INT1)
to Generate
(Continued)
l k
D9
D9
D9
e
N
Negative
e
Sign
Timer Preset Value
D8
D8
D8
32
INT7
D7
D7
D7
D6
D6
D6
X
INT5
D5
D5
D5
e
INT4
D4
D4
D4
Inputs higher than limit generate
Limit
INT3
D3
D3
D3
INT2
D2
D2
D2
INT1
D1
D1
D1
INT0
D0
D0
D0

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