LM12434CIWM NSC [National Semiconductor], LM12434CIWM Datasheet - Page 33

• Manufacturer Part Number: LM12434CIWM
• Description: Sign Data Acquisition System with Serial I/O and Self-Calibration
• Manufacturer: NSC [National Semiconductor]

D15
D15
D15
6 0 Operational Information
FIFO REGISTER (Read only)
D11 –D0
D12
D15–D13 Instruction number associated with the conversion result or the extended sign bit for 2’s complement arithmetic
INTERRUPT STATUS REGISTER (Read only)
Bits
the interrupt is enabled or disabled in the Interrupt Enable register The bits are reset to 0 when the register is read or by a
device reset through the Configuration register
D0
D1
D2
D3
D4
D5
D6
D7
D10–D8
D15–D11 Holds the number of conversion results that have been put in the FIFO but that have not yet been read by the user
LIMIT STATUS REGISTER (Read only)
The bits in this register are limit flags (vectors) that will be set to 1 when a limit is passed The bits are associated to individual
instruction limits as indicated below
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 Limit
D11 Limit
D12 Limit
D13 Limit
D14 Limit
D15 Limit
Instruction Number
or Extended Sign
Limit
Limit
Limit
Limit
Limit
Limit
Limit
Limit
Limit
Limit
0 to 7 are interrupt flags (vectors) that will be set to 1 when the following conditions occur The bits are set to 1 whether
Number of Unread Results
D14
D14
D14
Conversion Result
For 12-bit
For 8-bit
Sign Conversion result sign bit 0
selected by bit D5 (Channel Mask) of the Configuration register
INST0 Is set to 1 when a limit is passed in watchdog mode
INST1 Is set to 1 when the sequencer has loaded the instruction number contained in bits D10 D9 and D8 of the
Interrupt Enable register
INST2 Is set to 1 when number of conversion results in FIFO is equal to the programmed value (D15– D11) in the
Interrupt Enable Register
INST3 Is set to 1 when an auto-zero cycle is completed
INST4 Is set to 1 when a full calibraton cycle is completed
INST5 Is set to 1 when a pause condition is encountered
Don’t care
INST7 Is set to 1 when the chip is returned from standby and is ready
Holds the instruction number presently being executed or will be executed following a Pause or Timer delay
1 of Instruction
1 of Instruction
1 of Instruction
1 of Instruction
1 of Instruction
1 of Instruction
1 of Instruction
1 of Instruction
2 of Instruction
2 of Instruction
2 of Instruction
2 of Instruction
2 of Instruction
2 of Instruction
2 of Instruction
2 of Instruction
in FIFO
D13
D13
D13
FIGURE 9 Bit Assignments for LM12434 and LM12 L 438 Internal Registers (Continued)
a
a
Limit
Sign
D12
D12
D12
sign 12-bit result value
sign D11–D4
2 Status
0 is passed
1 is passed
2 is passed
3 is passed
4 is passed
5 is passed
6 is passed
7 is passed
0 is passed
1 is passed
2 is passed
3 is passed
4 is passed
5 is passed
6 is passed
7 is passed
D11
D11
D11
e
D10
D10
D10
result value D3– D0
Instruction Number
Being Executed
e
(Continued)
Positive 1
D9
D9
D9
D8
D8
D8
e
33
Negative
e
INST7
D7
1110
D7
D7
Conversion Result
D6
D6
D6
X
INST5
D5
D5
D5
INST4
Limit
D4
D4
D4
1 Status
INST3
D3
D3
D3
INST2
D2
D2
D2
INST1
D1
D1
D1
INST0
D0
D0
D0