LM12434CIWM NSC [National Semiconductor], LM12434CIWM Datasheet - Page 34

• Manufacturer Part Number: LM12434CIWM
• Description: Sign Data Acquisition System with Serial I/O and Self-Calibration
• Manufacturer: NSC [National Semiconductor]

6 0 Operational Information
Bits 12 –15 store the user-programmable acquisition time
The Sequencer keeps the internal S H in the acquisition
mode for a fixed number of clock cycles (nine clock cycles
for 12-bit
variable number of clock cycles equal to twice the value
stored in Bits 12 –15 Thus the S H’s acquisition time is (9
2D) clock cycles for 8-bit
dog’’ comparisons where D is the value stored in Bits 12–
15 The minimum acquisition time compensates for the typi-
cal internal multiplexer series resistance of 2 k
additional delay created by Bits 12–15 compensates for
source resistances greater than 60
acquisition time is determined by the source impedance at
the multiplexer input If the source resistance R
and the clock frequency is 8 MHz the value stored in bits
12 –15 (D) can be 0000 If R
tions determine the value that should be stored in
bits 12 –15
for 12-bits
for 8-bits
R
higher integer value If the value of 0 obtained from the
expressions above is greater than 15 it is advisable to lower
the source impedance by using an analog buffer between
the signal source and the LM12 L 438’s multiplexer inputs
The value of D can also be used to compensate for the
settling or response time of external processing circuits con-
nected between the LM12434’s MUXOUT and S H IN pins
a
a
S
Channel Selection Bits
in Instruction Register
2D) clock cycles for 12-bit
sign conversions or ‘‘watchdog’’ comparisons) plus a
is in k
Non-Inverting Input
D4 D3 D2
a
a
a
and f
000
001
010
011
100
101
110
111
sign conversions and two clock cycles for 8-bit
sign and ‘‘watchdog’’
sign
TABLE III LM12 L 438 Operating Mode Input Channel Selection through Input Multiplexer
CLK
D
D
is in MHz Round the result to the next
e
e
0 45 x R
0 36 x R
a
S l
a
sign conversions or ‘‘watch-
S
S
sign conversions and (2
x f
x f
60
CLK
CLK
Input Channel to Be
Non-Inverting Input
Connected to A D
80
the following equa-
(IN
The necessary
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
(Continued)
a
S k
)
Normal Operating Mode
and any
60
a
34
Instruction RAM Bank 2 RP
The second Instruction RAM section is selected by placing
‘‘01’’ in Bits 8 and 9 of the Configuration register
Bits 0– 7 hold ‘‘watchdog’’ limit
tion RAM ‘‘00’’ is set to a ‘‘1’’ the LM12434 and
LM12 L 438 performs a ‘‘watchdog’’ comparison of the
sampled analog input signal with the limit
followed by a comparison of the same sampled analog input
signal with the value found in limit
‘‘10’’)
Bit 8 holds limit
Bit 9’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt A ‘‘1’’ causes a voltage greater than
limit
age less than limit
Bits 10 – 15 are not used
Instruction RAM Bank 3 RP
The third Instruction RAM section is selected by placing
‘‘10’’ in Bits 8 and 9 of the Configuration register
Bits 0– 7 hold ‘‘watchdog’’ limit
tion RAM ‘‘00’’ is set to a ‘‘1’’ the LM12434 and
LM12 L 438 performs a ‘‘watchdog’’ comparison of the
sampled analog input signal with the limit
struction RAM ‘‘01’’) followed by a comparison of the same
sampled analog input signal with the value found in limit
Bit 8 holds limit
Bit 9’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt A ‘‘1’’ causes a voltage greater than
limit
age less than limit
Bits 10 – 15 are not used
Channel Selection Bits
in Instruction Register
Inverting Input
1 to generate an interrupt while a ‘‘0’’ causes a volt-
2 to generate an interrupt while a ‘‘0’’ causes a volt-
D7 D6 D5
000
001
010
011
100
101
110
111
1’s sign
2’s sign
1 to generate an interrupt
2 to generate an interrupt
e
e
01
10
1 When Bit 11 of Instruc-
2 When Bit 11 of Instruc-
Input Channel to Be
Connected to A D
Inverting Input
2 (Instruction RAM
(IN
1 value first (In-
GND
IN1
IN2
IN3
IN4
IN5
IN6
IN7
1 value first
b
)
2