PCA9525D NXP [NXP Semiconductors], PCA9525D Datasheet - Page 8

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PCA9525D

Manufacturer Part Number
PCA9525D
Description
Simple 2-wire bus buffer
Manufacturer
NXP [NXP Semiconductors]
Datasheet

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PCA9525
Product data sheet
Fig 9.
‘Hand over’ spikes on the data bus
This means that as direction control is handed from one side of the buffer to the other, a
voltage ‘spike’ of about V
became the ‘output’.
Figure 9
the SDA_IN port, with direction ‘hand over’ spike (upper left corner). The level of the
SDA_OUT port (channel 4) can be seen to increase as it goes from being held LOW by
the buffer, to being held LOW by another device on the bus.
Of course, the information on the SDA line is only latched into an I
clock edge. The spike on the data line does not occur at a time when data is being
latched, and thus the set-up and hold conditions are still met for a valid I
transaction.
Figure 9
drastic example is shown in
(SDA_OUT) is more lightly loaded than the side acting as the ‘output’ (SDA_IN). It
therefore rises quickly to V
Direction control briefly reverses, and SDA_OUT gets pulled back LOW again until
SDA_IN has exceeded V
also shows a glitch occurring on the SDA_OUT port (upper right corner). A more
shows clock and data being buffered through the PCA9525. Channel 3 shows
All information provided in this document is subject to legal disclaimers.
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Rev. 1 — 25 February 2011
IH
unlock
unlock
.
Figure
volts will appear on the side that was the ‘input’ and
level, before the SDA_IN has been able to exceed V
Fig 10. Fast rising SDA_xx ‘input’ side
10. In this case, the side acting as the ‘input’
Simple 2-wire bus buffer
2
C-bus device on a
PCA9525
© NXP B.V. 2011. All rights reserved.
2
C-bus
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8 of 22
IL
.

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