X9251-2.7 INTERSIL [Intersil Corporation], X9251-2.7 Datasheet - Page 5

• Manufacturer Part Number: X9251-2.7
• Description: Single Supply/Low Power/256-Tap/SPI Bus
• Manufacturer: INTERSIL [Intersil Corporation]

Figure 1. Detailed Potentiometer Block Diagram
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V
the potentiometer pins provided that V
more positive than or equal to V
V
always in effect.
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers,
one for each potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR#0) upon power-up. (See Figure 1.)
The wiper counter register is a volatile register; that is,
its contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the
value in DR#0 upon power-up, this may be different
CC
One of Four Potentiometers
≥ V
#: 0, 1, 2, or 3
IF WCR = 00[H] then R
IF WCR = FF[H] then R
H
, V
FROM INTERFACE
SERIAL DATA PATH
L
, V
CIRCUITRY
W
. The V
CC
and the voltages applied to
CC
W
W
5
is closet to R
is closet to R
ramp rate specification is
H
, V
DR#0
DR#2
L
L
H
, and V
CC
is always
8
W
, i.e.,
X9251
MODIFIED SCK
DR#1
DR#3
UP/DN
from the value present at power-down. Power-up
guidelines are recommended to ensure proper
loadings of the DR#0 value into the WCR#.
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a non-volatile operation and takes a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
– When WIP=0, indicates that no high-voltage write
8
is in progress.
cycle is in progress.
SERIAL
BUS
INPUT
UP/DN
CLK
PARALLEL
BUS
INPUT
REGISTER
COUNTER
INC/DEC
(WCR#)
WIPER
LOGIC
COUNTER
DECODE
- - -
CORE
DCP
September 14, 2005
R
R
R
H
W
L
FN8166.2