X9251-2.7 INTERSIL [Intersil Corporation], X9251-2.7 Datasheet - Page 6

• Manufacturer Part Number: X9251-2.7
• Description: Single Supply/Low Power/256-Tap/SPI Bus
• Manufacturer: INTERSIL [Intersil Corporation]

Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Non-volatile).
SERIAL INTERFACE
The X9251 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in, on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
I
The first byte sent to the X9251 from the host,
following a CS going HIGH to LOW, is called the
Identification Byte. The most significant four bits of the
Identification Byte are a Device Type Identifier, ID[3:0].
For the X9251, this is fixed as 0101 (refer to Table 3).
Table 3. Identification Byte Format
Table 4. Instruction Byte Format
DENTIFICATION
WCR7
(MSB)
(MSB)
(MSB)
(MSB)
Bit 7
ID3
I3
0
B
WCR6
YTE
Bit 6
ID2
I2
1
Device Type
Instruction
Opcode
Identifier
6
WCR5
Bit 5
ID1
I1
0
WCR4
Bit 4
ID0
I0
1
X9251
WCR3
Bit 3
The least significant four bits of the Identification Byte
are the Slave Address bits, AD[3:0]. For the X9251, A3
is 0, A2 is 0, A1 is the logic value at the input pin A1,
and A0 is the logic value at the input pin A0. Only the
device which Slave Address matches the incoming
bits sent by the master executes the instruction. The
A1 and A0 inputs can be actively driven by CMOS
input signals or tied to V
I
The next byte sent to the X9251 contains the instruction
and register pointer information. The four most significant
bits are used provide the instruction opcode (I[3:0]). The
RB and RA bits point to one of the four Data Registers of
each associated XDCP. The least two significant bits
point to one of four Wiper Counter Registers or
DCPs.The format is shown below in Table 4.
RB
A3
NSTRUCTION
0
Selection
Register
WCR2
Bit 2
RA
A2
B
0
YTE
Slave Address
Logic Value
CC
Pin A1
WCR1
or V
Bit 1
A1
P1
(WCR Selection)
DCP Selection
SS
.
Logic Value
Pin A0
(LSB)
(LSB)
WCR0
September 14, 2005
(LSB)
(LSB)
Bit 0
A0
P0
FN8166.2