DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 42

no-image

DSP56303

Manufacturer Part Number
DSP56303
Description
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSP56303AG100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
DSP56303AG100B1
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
DSP56303AG100R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
DSP56303GC100
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
DSP56303PV100
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
DSP56303PV100B
Manufacturer:
MOT
Quantity:
5 510
Part Number:
DSP56303PV100B
Manufacturer:
MAXIM
Quantity:
5 510
Part Number:
DSP56303VF100
Manufacturer:
MNDSPEED
Quantity:
2
Part Number:
DSP56303VF100
Manufacturer:
MOTOLOLA
Quantity:
513
Part Number:
DSP56303VF100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
DSP56303VF100
Manufacturer:
FREESCALE
Quantity:
624
Part Number:
DSP56303VF100
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
DSP56303VL100
Manufacturer:
FUJI
Quantity:
1 000
Signals/Connections
2.12 JTAG/OnCE Interface
2-18
TIO1
TIO2
Notes: 1.
TCK
TDI
TDO
TMS
TRST
Signal
Signal Name
Name
Input or
Output
Input or
Output
The Wait processing state does not affect the signal state.
Type
Input
Input
Output
Input
Input
Type
Input
Input
Reset
Table 2-15. Triple Timer Signals (Continued)
State During
Input
Input
Tri-stated
Input
Input
State During
Table 2-16. JTAG/OnCE Interface
Disconnected
Disconnected
internally
internally
Reset
Stop
DSP56303 User’s Manual, Rev. 2
1
Test Clock
A test clock signal for synchronizing JTAG test logic. This input is 5
V tolerant.
Test Data Input
A test data serial signal for test instructions and data. TDI is
sampled on the rising edge of TCK and has an internal pull-up
resistor. This input is 5 V tolerant.
Test Data Output
A test data serial signal for test instructions and data. TDO can be
tri-stated. The signal is actively driven in the shift-IR and shift-DR
controller states and changes on the falling edge of TCK. This pin is
5 V tolerant.
Test Mode Select
Sequences the test controller’s state machine, is sampled on the
rising edge of TCK, and has an internal pull-up resistor. This input is
5 V tolerant.
Test Reset
Asynchronously initializes the test controller, has an internal pull-up
resistor, and must be asserted after power up. This input is 5 V
tolerant.
Timer 1 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO1 is
input. In Watchdog, Timer, or Pulse Modulation mode, TIO1 is
output. The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output through
the Timer 1 Control/Status Register (TCSR1). This input is 5 V
tolerant.
Timer 2 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO2 is
input. In Watchdog, Timer, or Pulse Modulation mode, TIO2 is
output. The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output through
the Timer 2 Control/Status Register (TCSR2). This input is 5 V
tolerant.
Signal Description
Signal Description
Freescale Semiconductor

Related parts for DSP56303