XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 118

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Output Clock Jitter
Table 56: Output Clock Jitter
Output Clock Phase Alignment
Table 57: Output Clock Phase Alignment
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. Use the Jitter Calculator on the Xilinx website (http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm) for CLKFX and
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
3. Specification also applies to PSCLK.
Clock Synthesis Period Jitter
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
Phase Offset Between Any DCM Outputs
All CLK* outputs
Duty Cycle Precision
DLL outputs
CLKFX outputs
CLKFX180 output jitter.
DUTY_CYCLE_CORRECTION = TRUE.
Description
Description
(1)
R
CLKOUT_DUTY_CYCLE_DLL
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
CLKOUT_DUTY_CYCLE_FX
CLKIN_CLKFB_PHASE
CLKOUT_PHASE
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_FX
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_0
Symbol
Symbol
www.xilinx.com
(2)
Constraints
Constraints
Note (1)
±140
±150
±100
±50
±100
±150
±150
±150
±200
±150
±300
–7
–7
Speed Grade
Speed Grade
Note (1)
±140
±150
±100
±100
±150
±150
±150
±200
±150
±300
±50
–6
–6
Note (1)
±140
±100
±150
±100
±150
±150
±150
±200
±150
±300
±50
–5
–5
Module 3 of 4
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
47